SMPTE-259M/DVB-ASI Descrambler/Framer-Controller. CY7C9335A Datasheet

CY7C9335A Descrambler/Framer-Controller. Datasheet pdf. Equivalent

Part CY7C9335A
Description SMPTE-259M/DVB-ASI Descrambler/Framer-Controller
Feature CY7C9335A SMPTE-259M/DVB-ASI Descrambler/Framer-Controller Features • Fully compatible with SMPTE-2.
Manufacture Cypress Semiconductor
Datasheet
Download CY7C9335A Datasheet

CY7C9335A SMPTE-259M/DVB-ASI Descrambler/Framer-Controller CY7C9335A Datasheet
Recommendation Recommendation Datasheet CY7C9335A Datasheet




CY7C9335A
CY7C9335A
SMPTE-259M/DVB-ASI
Descrambler/Framer-Controller
Features
• Fully compatible with SMPTE-259M
• Fully compatible with DVB-ASI
• Operates from a single +5V supply
• 100-pin TQFP package
• Decodes 10-bit parallel digital streams for 27M
characters/sec (270 Mbits/sec serial)
• Operates with CY7B9334 SMPTE HOTLinkdeseri-
alizer/receiver
• X9 + X4 + 1 descrambler and NRZI-to-NRZ decoder may
be bypassed for raw data output
www.DataSheet4U.com
Functional Description
SMPTE-259M Operation
The CY7C9335A is a CMOS integrated circuit designed to
decode SMPTE-125M bit-parallel digital characters (or other
data formats) using the SMPTE-259M decoding rules.
Following decoding, the characters are framed by locating the
30-bit TRS pattern in the parallel character stream. The
framed characters are then output.
The inputs of the CY7C9335A are designed to be directly
mated to a CY7B9334 HOTLink receiver, which converts the
SMPTE-259M compatible high-speed serial data stream into
10-bit parallel characters.
This device performs both TRS (sync) detection and framing,
data descrambling with the SMPTE-259M X9+X4+1 algorithm,
and NRZI-to-NRZ decoding. These functions operate at a 27
MHz character rate. For those systems operating with
non-SMPTE-259M compliant video streams (or for diagnostic
purposes), the descrambler and NRZI decoding functions can
be disabled.
DVB-ASI Operation
The CY7C9335A also contains the necessary multiplexers,
control inputs and outputs, to control a DVB-ASI-compliant
video stream. DVB-ASI operation is enabled through
activation of a single input signal. This allows a single
serial-to-parallel input port to support both SMPTE and DVB
data streams under software or hardware control.
In DVB-ASI mode the CY7C9335A automatically enables both
the 8B/10B decoder and multibyte framer present in the
CY7B9334 receiver/deserializer. All error detection, fill, and
command codes are detected and output by the CY7C9335A.
The CY7C9335A operates from a single +5V supply. It is
available in a 100-pin TQFP space saving package.
Logic Block Diagram
D9(RVS)
D8
D7
D6
D5
D4
D3
D2
D1
D0(SC/D)
SYNC_EN
BYPASS
DVB_EN
CKR
OE
19 10
10
11 10
10
4
RF
A/B
PD9(SVS)
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0(SC/D)
H_SYNC
SYNC_ERR
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-02083 Rev. **
Revised October 13, 2003



CY7C9335A
Pin Configuration
TQFP
Top View
www.DataSheet4U.com
VSS
VSS
NC
NC
NC
NC
NC
NC
NC
OE
VSS
VCC
NC
VSS
VSS
BYPASS
NC
NC
SYNC_EN
NC
NC
DVB_EN
NC
VCC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
CY7C9335A
75 VSS
74 VCC
73 NC
72 NC
71 NC
70 NC
69 NC
68 NC
67 NC
66 NC
65 CKR
64 VSS
63 NC
62 VCC
61 VSS
60 NC
59 NC
58 SYNC_ERR
57 NC
56 H_SYNC
55 NC
54 NC
53 NC
52 VSS
51 NC
Pin Descriptions CY7C9335A SMPTE-259M Decoder
Name
BYPASS
RF
A/B
H_SYNC
I/O
Input
Output
Output
Output
Description
Bypass SMPTE decoding. BYPASS is ignored if DVB_EN is active (LOW). If BYPASS is HIGH at the
rising edge of CKR (and DVB_EN is HIGH), the data latched into the input register is routed around both
the NRZI decoder and the SMPTE descrambler and presented to the output register. If BYPASS is LOW
at the rising edge of the CKR clock (and DVB_EN is HIGH), the data present in the input register is routed
through the NRZI decoder and SMPTE scrambler.
Reframe. This output is the inverted DVB-EN signal.
CY7B9334 Port Select. When in DVB-ASI mode, this output will alternately select either the INA± or
INB± receiver port based on errors detected in the data stream. This allows CY7C9335A to operate with
normal and inverted DVB-ASI data streams (as would be commonly found on DVB-ASI streams routed
through SMPTE switches). This requires the CY7B9334 INA± and INB± inputs to be connected to the
same signal, but with INB± connected to invert the signal.
Horizontal Sync. This output toggles once every time that the TRS field is recognized. It changes state
one clock cycle prior to the first character of the TRS field (3FF in 10-bit hex) appearing at the PD09
outputs. This output also toggles to indicate detection of a TRS sequence, even when the TRS characters
are at a different offset from the present offset and SYNC_EN is active (HIGH). This toggling action is
disabled when DVB_EN is active (LOW).
Document #: 38-02083 Rev. **
Page 2 of 8





@ 2014 :: Datasheetspdf.com :: Semiconductors datasheet search & download site (Privacy Policy & Contact)