HYI25D512160C

November 2006 HYI25D512160C[C/E/F/T] www.DataSheet4U.com 5 1 2 - M b i t D o u b l e - D a t a - R a t e SD R A M DDR SDRAM Internet Data Sheet Rev. 1.0 Internet Data Sheet HYI25D512160C[C/E/F/T] 512-Mbit Double-Data-Rate SDRAM HYI25D512160C[C/E/F/T] Revision History: 2006-11, Rev. 1.0 Page www.DataSheet4U.com Subjects (major changes since last revision) Adapted internet edition Qimonda update, first final revision All All We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 11082006-S9OT-UFSN 2 Internet Data Sheet HYI25D512160C[C/E/F/T] 512-Mbit Double-Data-Rate SDRAM 1 www.DataSheet4U.com Overview This chapter gives an overview of the 512-Mbit Double-Data-Rate SDRAM product family and describes its main characteristics. 1.1 Features Double data rate architecture: two data transfers per clock cycle Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver DQS is edge-aligned with data for reads and is center-aligned with data for writes Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK tran...