HYI39S512160A

June 2007 HY[B/I]39S512400A[E/T] HY[B/I]39S512800A[E/T] HY[B/I]39S512160A[E/T] www.DataSheet4U.com 512-Mbit Synchronous DRAM SDRAM RoHS Compliant Products Internet Data Sheet Rev. 1.52 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM HY[B/I]39S512400A[E/T], HY[B/I]39S512800A[E/T], HY[B/I]39S512160A[E/T] Revision History: 2007-06, Rev. 1.52 Page All 13 www.DataSheet4U.com 13 15 19 21 Subjects (major changes since last revision) Adapted internet edition Corrected operation command "Power Down / Clock suspend ...” in truth table Corrected operation command "Power Down Exit" to X (WE#) Corrected text to "After the mode register is set a NOP command is required" , chapter 3.3 Corrected text to "One clock delay is required for mode entry and exit", chapter 3.5 Corrected the line "Input Capacitances: CK" in table 10, chapter 4 Qimonda template Previous Revision: 2007-05, Rev. 1.5 All Added more product types Previous Revision: 2006-01, Rev. 1.4 Previous Revision: 2007-06, Rev. 1.51 We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: [email protected] qag_techdoc_rev400 / 3.2 QAG / 2006-07-21 03292006-6Y91-0T2Z 2 Internet Data Sheet HY[I/B]39S512[40/80/16]0A[E/T] 512-Mbit Synchronous DRAM 1 w w w Overview D a t a S h Features e e...