MOS FET. 2SJ598 Datasheet

2SJ598 FET. Datasheet pdf. Equivalent

Part 2SJ598
Description SWITCHING P-CHANNEL POWER MOS FET
Feature DATA SHEET MOS FIELD EFFECT TRANSISTOR 2SJ598 SWITCHING P-CHANNEL POWER MOS FET DESCRIPTION The 2.
Manufacture NEC
Datasheet
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DATA SHEET MOS FIELD EFFECT TRANSISTOR 2SJ598 SWITCHING P- 2SJ598 Datasheet
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2SJ598
DATA SHEET
MOS FIELD EFFECT TRANSISTOR
2SJ598
SWITCHING
P-CHANNEL POWER MOS FET
DESCRIPTION
The 2SJ598 is P-channel MOS Field Effect Transistor designed
for solenoid, motor and lamp driver.
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FEATURES
Low on-state resistance:
RDS(on)1 = 130 mMAX. (VGS = –10 V, ID = –6 A)
RDS(on)2 = 190 mMAX. (VGS = –4.0 V, ID = –6 A)
Low Ciss: Ciss = 720 pF TYP.
Built-in gate protection diode
TO-251/TO-252 package
ORDERING INFORMATION
PART NUMBER
PACKAGE
2SJ598
TO-251 (MP-3)
2SJ598-Z
TO-252 (MP-3Z)
ABSOLUTE MAXIMUM RATINGS (TA = 25°C)
Drain to Source Voltage (VGS = 0 V)
VDSS
–60
Gate to Source Voltage (VDS = 0 V)
Drain Current (DC) (TC = 25°C)
Drain Current (pulse) Note1
Total Power Dissipation (TC = 25°C)
VGSS
ID(DC)
ID(pulse)
PT
m20
m12
m30
23
Total Power Dissipation (TA = 25°C)
PT 1.0
Channel Temperature
Tch 150
Storage Temperature
Single Avalanche Current Note2
Single Avalanche Energy Note2
Tstg –55 to +150
IAS –12
EAS 14.4
V
V
A
A
W
W
°C
°C
A
mJ
(TO-251)
(TO-252)
Notes 1. PW 10 µs, Duty Cycle 1%
2. Starting Tch = 25°C, VDD = –30 V, RG = 25 , VGS = –20 0 V
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
Document No. D14656EJ4V0DS00 (4th edition)
Date Published August 2004 NS CP(K)
Printed in Japan
The mark shows major revised points.
2000, 2001



2SJ598
2SJ598
ELECTRICAL CHARACTERISTICS (TA = 25°C)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
Zero Gate Voltage Drain Current
Gate Leakage Current
Gate Cut-off Voltage
IDSS
IGSS
VGS(off)
VDS = –60 V, VGS = 0 V
VGS = m16 V, VDS = 0 V
VDS = –10 V, ID = –1 mA
Forward Transfer Admittance
| yfs | VDS = –10 V, ID = –6 A
Drain to Source On-state Resistance
RDS(on)1 VGS = –10 V, ID = –6 A
RDS(on)2 VGS = –4.0 V, ID = –6 A
Input Capacitance
Ciss VDS = –10 V
Output Capacitance
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Reverse Transfer Capacitance
Coss
Crss
VGS = 0 V
f = 1 MHz
Turn-on Delay Time
td(on)
ID = –6 A
Rise Time
tr VGS = –10 V
Turn-off Delay Time
td(off)
VDD = –30 V
Fall Time
tf RG = 0
Total Gate Charge
QG ID = –12 A
Gate to Source Charge
QGS VDD= –48 V
Gate to Drain Charge
QGD
VGS = –10 V
Body Diode Forward Voltage
VF(S-D) IF = 12 A, VGS = 0 V
Reverse Recovery Time
trr IF = 12 A, VGS = 0 V
Reverse Recovery Charge
Qrr di/dt = 100 A /µs
MIN.
–1.5
5
TYP. MAX.
–10
m10
–2.0 –2.5
11
102 130
131 190
720
150
50
7
4
35
10
15
3
4
0.98
50
100
UNIT
µA
µA
V
S
m
m
pF
pF
pF
ns
ns
ns
ns
nC
nC
nC
V
ns
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25
L
PG.
VGS = 20 0 V
50
VDD
IAS BVDSS
VDS
ID
VDD
Starting Tch
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
RG
PG.
VGS()
0
τ
τ = 1 µs
Duty Cycle 1%
RL
VDD
VGS()
VGS
Wave Form
0 10%
VDS()
90%
VDS
VDS
Wave Form 0
td(on)
VGS 90%
90%
10% 10%
tr td(off)
tf
ton toff
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
PG. 50
RL
VDD
2 Data Sheet D14656EJ4V0DS





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