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Control Hub. ICS9LPR426A Datasheet

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Control Hub. ICS9LPR426A Datasheet






ICS9LPR426A Hub. Datasheet pdf. Equivalent




ICS9LPR426A Hub. Datasheet pdf. Equivalent





Part

ICS9LPR426A

Description

Low Power Programmable Timing Control Hub



Feature


Integrated Circuit Systems, Inc. ICS9LP R426A Advance Information Low Power Pr ogrammable Timing Control Hub™ for P4 ™ processor Key Specifications: • C PU outputs cycle-cycle jitter < 85ps PCIEX outputs cycle-cycle jitter < 12 5ps Output Features: • SATA outputs c ycle-cycle jitter < 125ps • 2 - 0.7V push-pull differential CPU pairs • PC I outputs cycle-cycle jitter < 5.
Manufacture

Integrated Circuit Systems

Datasheet
Download ICS9LPR426A Datasheet


Integrated Circuit Systems ICS9LPR426A

ICS9LPR426A; 00ps • 5 - 0.7V push-pull differential PCIEX pairs • +/- 100ppm frequency a ccuracy on CPU, PCIEX and SATA clocks 1 - 0.7V push-pull differential SATA pair +/- 100ppm frequency accuracy on USB clocks • 1 - 0.7V push-pull diffe rential CPU/PCIEX selectable pair • w ww.DataSheet4U.com • 1 - 0.7V push-pu ll differential 27MHz/LCDCLK/PCIEX Feat ures/Benefits: selectable pair.


Integrated Circuit Systems ICS9LPR426A

• Supports tight ppm accuracy clocks for Serial-ATA and • 4 - PCI (33MHz) PCIEX • 2 - PCICLK_F, (33MHz) free-ru nning • Supports programmable spread percentage and • 1 - USB, 48MHz frequ ency • 2 - REF, 14.318MHz • Uses ex ternal 14.318MHz crystal, external crys tal load caps are required for frequenc y tuning • PEREQ# pins to support PCI EX power management. • Low power d.


Integrated Circuit Systems ICS9LPR426A

ifferential clock outputs (No 50W resist or to GND needed) Recommended Applicati on: Low Power CK410M Compliant Main Clo ck Pin Configuration VDDPCI GND PCICLK 3 PCICLK4 *SELPCIEX0_LCD#PCICLK5 GND VD DPCI ITP_EN/PCICLK_F0 *SELLCD_27#/PCICL K_F1 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHzL DOTC_96MHzL FSLB/TEST_ MODE 27FIX/LCD_SSCGT/PCIeT_L0 27SS/LCD_ SSCGC/PCIeC_L0 1 2.

Part

ICS9LPR426A

Description

Low Power Programmable Timing Control Hub



Feature


Integrated Circuit Systems, Inc. ICS9LP R426A Advance Information Low Power Pr ogrammable Timing Control Hub™ for P4 ™ processor Key Specifications: • C PU outputs cycle-cycle jitter < 85ps PCIEX outputs cycle-cycle jitter < 12 5ps Output Features: • SATA outputs c ycle-cycle jitter < 125ps • 2 - 0.7V push-pull differential CPU pairs • PC I outputs cycle-cycle jitter < 5.
Manufacture

Integrated Circuit Systems

Datasheet
Download ICS9LPR426A Datasheet




 ICS9LPR426A
Integrated
Circuit
Systems, Inc.
ICS9LPR426A
Advance Information
Low Power Programmable Timing Control Hub™ for P4™ processor
Recommended Application:
Low Power CK410M Compliant Main Clock
Output Features:
• 2 - 0.7V push-pull differential CPU pairs
• 5 - 0.7V push-pull differential PCIEX pairs
• 1 - 0.7V push-pull differential SATA pair
www.DataSheet4U.c1om- 0.7V push-pull differential CPU/PCIEX selectable pair
• 1 - 0.7V push-pull differential 27MHz/LCDCLK/PCIEX
selectable pair
• 4 - PCI (33MHz)
• 2 - PCICLK_F, (33MHz) free-running
• 1 - USB, 48MHz
• 2 - REF, 14.318MHz
Key Specifications:
• CPU outputs cycle-cycle jitter < 85ps
• PCIEX outputs cycle-cycle jitter < 125ps
• SATA outputs cycle-cycle jitter < 125ps
• PCI outputs cycle-cycle jitter < 500ps
• +/- 100ppm frequency accuracy on CPU, PCIEX and
SATA clocks
• +/- 100ppm frequency accuracy on USB clocks
Features/Benefits:
• Supports tight ppm accuracy clocks for Serial-ATA and
PCIEX
• Supports programmable spread percentage and
frequency
• Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
• PEREQ# pins to support PCIEX power management.
• Low power differential clock outputs (No 50W resistor
to GND needed)
Pin Configuration
VDDPCI 1
GND 2
PCICLK3 3
PCICLK4 4
*SELPCIEX0_LCD#PCICLK5 5
GND 6
VDDPCI 7
ITP_EN/PCICLK_F0 8
*SELLCD_27#/PCICLK_F1 9
Vtt_PwrGd#/PD 10
VDD48 11
FSLA/USB_48MHz 12
GND 13
DOTT_96MHzL 14
DOTC_96MHzL 15
FSLB/TEST_MODE 16
27FIX/LCD_SSCGT/PCIeT_L0 17
27SS/LCD_SSCGC/PCIeC_L0 18
PCIeT_L1 19
PCIeC_L1 20
VDDPCIEX 21
PCIeT_L2 22
PCIeC_L2 23
PCIeT_L3 24
PCIeC_L3 25
SATACLKT_L 26
SATACLKC_L 27
VDDPCIEX 28
56 PCICLK2/REQ_SEL**
55 PCI&PCIEX_STOP#
54 CPU_STOP#
53 REF1/FSLC/TEST_SEL
52 REF0
51 GND
50 X1
49 X2
48 VDDREF
47 SDATA
46 SCLK
45 GND
44 CPUT_L0
43 CPUC_L0
42 VDDCPU
41 CPUT_L1
40 CPUC_L1
39 VDD
38 GNDA
37 VDDA
36 CPUITPT_L2/PCIeT_L6
35 CPUITPC_L2/PCIeC_L6
34 VDDPCIEX
33 PEREQ1#/PCIeT_L5
32 PEREQ2#/PCIeC_L5
31 PCIeT_L4
30 PCIeC_L4
29 GND
56-TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
1346–10/23/07
Functionality Table
Bit 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit 2 Bit 1 Bit 0
Bit 3
FSLC FSLB FSLA
CPU
MHz
PCIEX
MHz
0 0 0 0 266.66 99.75
0 0 0 1 133.33 99.75
0 0 1 0 200.00 99.75
0 0 1 1 166.66 99.75
0 1 0 0 333.33 99.75
0 1 0 1 100.00 99.75
0 1 1 0 400.00 99.75
0 1 1 1 200.00 99.75
1 0 0 0 266.66 99.75
1 0 0 1 133.33 99.75
1 0 1 0 200.00 99.75
1 0 1 1 166.66 99.75
1 1 0 0 333.33 99.75
1 1 0 1 100.00 99.75
1 1 1 0 400.00 99.75
1 1 1 1 200.00 99.75
0 0 0 0 269.33 100.75
0 0 0 1 271.99 101.75
0 0 1 0 274.66 102.74
0 0 1 1 277.33 103.74
0 1 0 0 279.99 104.74
0 1 0 1 282.66 105.74
0 1 1 0 285.33 106.73
0 1 1 1 287.99 107.73
1 0 0 0 269.33 108.73
1 0 0 1 271.99 109.73
1 0 1 0 274.66 110.72
1 0 1 1 277.33 111.72
1 1 0 0 279.99 112.72
1 1 0 1 282.66 113.72
1 1 1 0 285.33 114.71
1 1 1 1 287.99 115.71
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
SATA
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.




 ICS9LPR426A
Integrated
Circuit
Systems, Inc.
ICS9LPR426A
Advance Information
Pin Description
PIN #
1
2
PIN NAME
VDDPCI
GND
3 PCICLK3
4 PCICLK4
5 *SELPCIEX0_LCD#PCICLK5
6 GND
7 VDDPCI
www.DataSheet4U.com
8 ITP_EN/PCICLK_F0
9 *SELLCD_27#/PCICLK_F1
10 Vtt_PwrGd#/PD
11 VDD48
12 FSLA/USB_48MHz
13 GND
14 DOTT_96MHzL
15 DOTC_96MHzL
16 FSLB/TEST_MODE
17 27FIX/LCD_SSCGT/PCIeT_L0
18 27SS/LCD_SSCGC/PCIeC_L0
19 PCIeT_L1
20 PCIeC_L1
21 VDDPCIEX
22 PCIeT_L2
23 PCIeC_L2
24 PCIeT_L3
25 PCIeC_L3
26 SATACLKT_L
27 SATACLKC_L
28 VDDPCIEX
TYPE
PWR
PWR
OUT
OUT
I/O
PWR
PWR
I/O
I/O
IN
PWR
I/O
PWR
OUT
OUT
IN
OUT
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Latched select input for LCDCLK/PCIEX output 0 = LCDCLK, 1 = PCIEX / 3.3V PCI clock
output.
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select pin functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP#.
SELLCD_27#: latched input to select pin functionality
1 = LCDCLK pair
0 = 27MHzSS/27MHzSS# pair
Vtt_PwrGd# is an active low input used to determine when latched inputs are ready to be
sampled. PD is an asynchronous active high input pin used to put the device into a low
power state. The internal clocks, PLLs and the crystal oscillator are stopped.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V.
Ground pin.
True clock of low power differential pair for 96.00MHz DOT clock. No 50ohm to GND
needed.
Complement clock of low power differential pair for 96.00MHz DOT clock. No 50ohm
resistor to GND needed.
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics
for Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z
and REF/N divider mode while in test mode. Refer to Test Clarification Table.
27MHz Non-Spread Push-Pull output / True clock of low power LCDCLK output / True
clock of low power PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
27MHz Spreading Push-Pull output / Complementary clock of LCDCLK_SS output /
Complementary clock of PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
Power supply for PCI Express clocks, nominal 3.3V
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
True clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed)
Complement clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND
needed)
Power supply for PCI Express clocks, nominal 3.3V
1346—10/23/07
2




 ICS9LPR426A
Integrated
Circuit
Systems, Inc.
ICS9LPR426A
Advance Information
Pin Description (Continued)
PIN #
PIN NAME
29 GND
30 PCIeC_L4
31 PCIeT_L4
32 PEREQ2#/PCIeC_L5
www.DataSheet4U.3c3om PEREQ1#/PCIeT_L5
34 VDDPCIEX
35 CPUITPC_L2/PCIeC_L6
36 CPUITPT_L2/PCIeT_L6
37 VDDA
38 GNDA
39 VDD
40 CPUC_L1
41 CPUT_L1
42 VDDCPU
43 CPUC_L0
44 CPUT_L0
45 GND
46 SCLK
47 SDATA
48 VDDREF
49 X2
50 X1
51 GND
52 REF0
53 REF1/FSLC/TEST_SEL
54 CPU_STOP#
55 PCI&PCIEX_STOP#
56 PCICLK2/REQ_SEL**
TYPE
PWR
OUT
OUT
I/O
I/O
PWR
OUT
OUT
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
I/O
IN
IN
I/O
DESCRIPTION
Ground pin.
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to
GND needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND
needed)
Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 =
disabled, 0 = enabled. / Complement clock of differential low power PCI Express output.
No 50ohm resistor to GND needed.
Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 =
disabled, 0 = enabled. / True clock of differential low power PCI Express output. No
50ohm resistor to GND needed.
Power supply for PCI Express clocks, nominal 3.3V
Complement clock of differential pair CPU output. / Complement clock of differential
PCIEX pair. These are 0.8V push pull outputs. No 50ohm resistor to GND needed.
True clock of differential pair CPU output. / True clock of differential PCIEX pair. These
are 0.8V push pull outputs. No 50ohm resistor to GND needed.
3.3V power for the PLL core.
Ground pin for the PLL core.
Power supply, nominal 3.3V
Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor
to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs. No 50 ohm resistor to GND
needed.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor
to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND
needed.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched
input to enable test mode. Refer to Test Clarification Table
Stops all CPU clocks, except those set to be free running clocks
Stops all PCICLKs at logic 0 level, when low. Free running PCICLKs are not effected by
this input.
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
1346—10/23/07
3



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