ICS9LPR426A

Integrated Circuit Systems, Inc. ICS9LPR426A Advance Information Low Power Programmable Timing Control Hub™ for P4™ processor Key Specifications: CPU outputs cycle-cycle jitter < 85ps PCIEX outputs cycle-cycle jitter < 125ps Output Features: SATA outputs cycle-cycle jitter < 125ps 2 - 0.7V push-pull differential CPU pairs PCI outputs cycle-cycle jitter < 500ps 5 - 0.7V push-pull differential PCIEX pairs +/- 100ppm frequency accuracy on CPU, PCIEX and SATA clocks 1 - 0.7V push-pull differential SATA pair +/- 100ppm frequency accuracy on USB clocks 1 - 0.7V push-pull differential CPU/PCIEX selectable pair www.DataSheet4U.com 1 - 0.7V push-pull differential 27MHz/LCDCLK/PCIEX Features/Benefits: selectable pair Supports tight ppm accuracy clocks for Serial-ATA and 4 - PCI (33MHz) PCIEX 2 - PCICLK_F, (33MHz) free-running Supports programmable spread percentage and 1 - USB, 48MHz frequency 2 - REF, 14.318MHz Uses external 14.318MHz crystal, external crystal load caps are required for frequency tuning PEREQ# pins to support PCIEX power management. Low power differential clock outputs (No 50W resistor to GND needed) Recommended Application: Low Power CK410M Compliant Main Clock Pin Configuration VDDPCI GND PCICLK3 PCICLK4 *SELPCIEX0_LCD#PCICLK5 GND VDDPCI ITP_EN/PCICLK_F0 *SELLCD_27#/PCICLK_F1 Vtt_PwrGd#/PD VDD48 FSLA/USB_48MHz GND DOTT_96MHzL DOTC_96MHzL FSLB/TEST_MODE 27FIX/LCD_SSCGT/PCIeT_L0 27SS/LCD_SSCGC/PCIeC_L0 1 2 3 4 5 6 7 8 9 10 11...