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CXD8989R Dataheets PDF



Part Number CXD8989R
Manufacturers ETC
Logo ETC
Description CMOS A/V Data REC Processor
Datasheet CXD8989R DatasheetCXD8989R Datasheet (PDF)

C-MOS A/V DATA REC PROCESS (GATE ARRAY) - TOP VIEW 132 130 125 120 115 110 105 100 95 CXD8989R (1/4) IL11 VDD (+5 V) VDD (+5 V) GND GND GND 133 135 GND 140 GND 90 89 88 85 GND 80 www.DataSheet4U.com VDD (+5 V) 145 75 GND 150 70 GND VDD (+5 V) 155 65 160 GND GND 60 165 VDD (+5 V) VDD (+5 V) 55 170 GND GND 50 VDD (+5 V) GND GND GND GND 175 176 VDD (+5 V) 45 1 5 10 15 20 25 30 35 40 44 CXD8989R (2/4) (VDD = +5 V) PIN No. 1 2 3 4 5 6 7 8 9 10 www.Data.

  CXD8989R   CXD8989R


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********** C-MOS A/V DATA REC PROCESS (GATE ARRAY) - TOP VIEW 132 130 125 120 115 110 105 100 95 CXD8989R (1/4) IL11 VDD (+5 V) VDD (+5 V) GND GND GND 133 135 GND 140 GND 90 89 88 85 GND 80 www.DataSheet4U.com VDD (+5 V) 145 75 GND 150 70 GND VDD (+5 V) 155 65 160 GND GND 60 165 VDD (+5 V) VDD (+5 V) 55 170 GND GND 50 VDD (+5 V) GND GND GND GND 175 176 VDD (+5 V) 45 1 5 10 15 20 25 30 35 40 44 CXD8989R (2/4) (VDD = +5 V) PIN No. 1 2 3 4 5 6 7 8 9 10 www.DataSheet4U.com 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O O I I I I — I I I I O — O O O O — I I I I I I I I I I — O O O O — O O O O O — O O O O O SIGNAL DIAG AINT0 AINT1 PAY_EN AINT2 GND ADEN2 SW_DET PCERD IN_FP RX_INIT VDD DIAGRE DIAGRST ATRIWE ATRIRSTW GND S_DAT0 S_DAT1 S_DAT2 S_DAT3 S_DAT4 S_DAT5 S_DAT6 S_DAT7 S_DAT8 S_DAT9 GND WCCONT0 WCCONT1 WCCONT2 WCCONT3 VDD WCCONT4 MAIN_WE W_INIT M_RSTW H_REC GND GWDATA0 GWDATA1 GWDATA2 GWDATA3 GWDATA4 PIN No. 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 I/O O O O O O — O O O O O — O O O I — I I I I I I I I I I — I O O I — I I O O O — I I I I I SIGNAL GWDATA5 GWDATA6 GWDATA7 GWSYNC GWSTART GND GWEND WE_V WE_A WE_T RSTW_V VDD RSTW_A RSTW_T W_CKO W_CK GND GRDATA0 GRDATA1 GRDATA2 GRDATA3 GRDATA4 GRDATA5 GRDATA6 GRDATA7 GRSYNC GRSTART GND GREND RE_V RSTR_V XSM VDD XTST SDI SDO RE_A RSTR_A GND CADRS0 CADRS1 CADRS2 CADRS3 CADRS4 PIN No. 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 I/O I I I I I — I I/O I/O I/O I/O — I/O I/O I/O I/O — O O O O O O O O O O — O O O I — O O O O O — I I I I I SIGNAL CADRS5 CADRS6 CADRS7 CRD CWR GND CCS CDATA0 CDATA1 CDATA2 CDATA3 VDD CDATA4 CDATA5 CDATA6 CDATA7 GND DMA_DAT0 DMA_DAT1 DMA_DAT2 DMA_DAT3 DMA_DAT4 DMA_DAT5 DMA_DAT6 DMA_DAT7 DFWE1 DFWE2 GND DFWE3 DFWE4 DFRSTW DMA_DREQ VDD RCCONT0 RCCONT1 RCCONT2 RCCONT3 RCCONT4 GND R_DAT0 R_DAT1 R_DAT2 R_DAT3 R_DAT4 PIN No. 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 I/O I I I I I — O O O O O — O O O O — O O O O O O O O O O — O O O I — I I O O O — O O I I I SIGNAL R_DAT5 R_DAT6 R_DAT7 I_PORT0 I_PORT1 GND TEST_R PINT_RE0 PINT_RE1 PINT_RE2 PINT_RE3 VDD PINT_RE4 PINT_RE5 PINT_RE6 PINT_RE7 GND W_DAT0 W_DAT1 W_DAT2 W_DAT3 W_DAT4 W_DAT5 W_DAT6 W_DAT7 O_PORT0 O_PORT1 GND MAIN_RE P_INIT M_RSTR XACK VDD BCK XTCK TEST_W WCCONT5 RCCONT5 GND EXT_CS0 EXT_CS1 R_CK SG_FP SYS_RST CXD8989R (3/4) INPUT ADEN2, PAY_EN AINT0 AINT1 AINT2 BCK, XACK, XTCK CADRS0 - CADRS7 CCS CRD CWR DMA_DREQ GRDATA0 - GRDATA7 GREND GRSTART GRSYNC I_PORT0, I_PORT1 IN_FP, SG_FP PCERD R_CK R_DAT0 - R_DAT7 S_DAT0 - S_DAT10 SDI, XSM, XTST SW_DET SYS_RST W_CK www.DataSheet4U.com ; DATA ENABLE (SDDI RX) ; VIDEO/NON-AV INTERRUPT (SDDI RX) ; AUDIO INTERRUPT (SDDI RX) ; ATTRIBUTE INTERRUPT (SDDI RX) ; IC TEST PIN ; CPU ADDRESS BUS ; CPU CHIP SELECT ; CPU READ PULSE ; CPU WRITE PULSE ; DMA FIFO WRITE REQUEST ; GOP DELAY READ DATA IN ; GOP DELAY END PULSE ; GOP DELAY START PULSE ; GOP DELAY SYNC ; IN PORT ; FRAME PULSE IN ; PAYLOAD CRCC ERROR (SDDI RX) ; READ PROCESS CLOCK ; MAIN FIFO READ DATA IN ; DATA IN (SDDI RX) ; IC TEST PIN ; SWITCHING DETECT (SDDI RX) ; POWER ON RESET ; WRITE PROCESS CLOCK CXD8989R (4/4) OUTPUT ATRIRSTW ATRIWE DFRSTW DFWE1 - DFWE4 DIAG DIAGRE DIAGRST DMA_DAT0 - DMA_DAT7 EXT_CS0, EXT_CS1 GWDATA0 - GWDATA7 GWEND GWSTART GWSYNC H_REC M_RSTR M_RSTW MAIN_RE MAIN_WE O_PORT0, O_PORT1 P_INIT PINT_RE0 - PINT_RE7 RCCOUNT0 - RCCOUNT5 RE_A RE_V RSTR_A RSTR_V RSTW_A RSTW_T RSTW_V RX_INIT SDO TEST_R TEST_W W_CKO W_DAT0 - W_DAT7 W_INIT WCCOUNT0 - WCCOUNT5 WE_A WE_T WE_V INPUT/OUTPUT CDATA0 - CDATA7 www.DataSheet4U.com ; ATTRIBUTE FIFO RSTW ; ATTRIBUTE FIFO WRITE ENABLE ; DMA FIFO RSTW ; DMA FIFO WRITE ENABLE ; DIAG MODE SEL (H: DIAG MODE) ; DIAG FIFO READ ENABLE ; DIAG FIFO RSTR ; DMA FIFO WRITE DATA OUT ; CHIP SELECT OUT ; GOP DELAY WRITE DATA OUT ; GOP DELAY END PULSE OUT ; GOP DELAY START PULSE OUT ; GOP DELAY SYNC OUT ; REC LED DRIVE (H: REC) ; MAIN FIFO RSTR ; MAIN FIFO RSTW ; MAIN FIFO READ ENABLE ; MAIN FIFO WRITE ENABLE ; OUT PORT ; MAIN FIFO POWER ON INITIAL PULSE ; MAIN FIFO POWER ON INITIAL CHIP SELECT ; MAIN FIFO READ CHIP COUNTER OUT ; AUDIO FIFO READ ENABLE ; VIDEO FIFO READ ENABLE ; AUDIO FIFO RSTR ; VIDEO FIFO RSTR ; AUDIO FIFO RSTW ; TIME CODE FIFO RSTW ; VIDEO FIFO RSTW ; CPU INTERRUPT ; IC TEST PIN ; IC TEST ; IC TEST ; WRITE PROCESS CLOCK OUT ; MAIN FIFO WRITE DATA OUT ; MAIN FIFO POWER ON INITIAL PULSE ; MAIN FIFO WRITE CHIP COUNTER OUT ; AUDIO FIFO WRITE ENABLE ; TIME CODE FIFO WRITE ENABLE ; VIDEO FIFO WRITE ENABLE ; CPU DATA BUS 0 - 7 .


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