Communications Processor. 79RC32334 Datasheet

79RC32334 Datasheet PDF, Equivalent

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IDT Interprise Integrated Communications Processor


Integrated Device Technology

Total Page 30 Pages
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79RC32334 Datasheet
IDTTM InterpriseTM Integrated
Communications Processor
79RC32334—Rev. Y
RC32300 32-bit Microprocessor
– Up to 150 MHz operation
– Enhanced MIPS-II Instruction Set Architecture (ISA)
– Cache prefetch instruction
– Conditional move instruction
– DSP instructions
www.DataSheet4U.cSomupports big or little endian operation
– MMU with 32 page TLB
– 8kB Instruction Cache, 2-way set associative
– 2kB Data Cache, 2-way set associative
– Cache locking per line
– Programmable on a page basis to implement a write-through
no write allocate, write-through write allocate, or write-back
algorithms for cache management
– Compatible with a wide variety of operating systems
Local Bus Interface
– Up to 75 MHz operation
– 26-bit address bus
– 32-bit data bus
– Direct control of local memory and peripherals
– Programmable system watch-dog timers
– Big or little endian support
Interrupt Controller simplifies exception management
Four general purpose 32-bit timer/counters
Block Diagram
Programmable I/O (PIO)
– Input/Output/Interrupt source
– Individually programmable
SDRAM Controller (32-bit memory only)
– 4 banks, non-interleaved
– Up to 512MB total SDRAM memory supported
– Implements full, direct control of discrete, SODIMM, or DIMM
– Supports 16Mb through 512Mb SDRAM device depths
– Automatic refresh generation
Serial Peripheral Interface (SPI) master mode interface
UART Interface
– Two 16550 compatible UARTs
– Baud rate support up to 1.5 Mb/s
– Modem control signals available on one channel
Memory & Peripheral Controller
– 6 banks, up to 64MB per bank
– Supports 8-,16-, and 32-bit interfaces
– Supports Flash ROM, SRAM, dual-port memory, and
peripheral devices
– Supports external wait-state generation
– 8-bit boot PROM support
– Flexible I/O timing protocols
In-Circuit Emulator Interface
Enhanced MIPS-II ISA Compatible
Integer CPU
2-set, Lockable
Data Cache
Instr. Cache
Interrupt Control
32-bit Timers
DMA Control
Programmable I/O
SPI Control
PCI Bridge
Figure 1 RC32334 Block Diagram
Note: This data sheet does not apply to revision Z silicon. Contact your IDT sales representative for information on revision Z.
© 2004 Integrated Device Technology, Inc.
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc.
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79RC32334 Datasheet
IDT 79RC32334—Rev. Y
4 DMA Channels
– 4 general purpose DMA, each with endianess swappers and
byte lane data alignment
– Supports scatter/gather, chaining via linked lists of records
– Supports memory-to-memory, memory-to-I/O, memory-to-
PCI, PCI-to-PCI, and I/O-to-I/O transfers
– Supports unaligned transfers
– Supports burst transfers
– Programmable DMA bus transactions burst size
(up to 16 bytes)
PCI Bus Interface
– 32-bit PCI, up to 66 MHz
– Revision 2.2 compatible
– Target or master
www.DataSheet4––U.cHTomhorseteorslsoat tPelClitIearbiter
– Serial EEPROM support, for loading configuration registers
Off-the-shelf development tools
JTAG Interface (IEEE Std. 1149.1 compatible)
256-ball BGA (1.0mm spacing)
3.3V operation with 5V tolerant I/O
EJTAG in-circuit emulator interface
Device Overview
The IDT RC32334 device is an integrated processor based on the
RC32300 CPU core. This product incorporates a high-performance, low-
cost 32-bit CPU core with functionality common to a large number of
embedded applications. The RC32334 integrates these functions to
enable the use of low-cost PC commodity market memory and I/O
devices, allowing the aggressive price/performance characteristics of
the CPU to be realized quickly into low-cost systems.
CPU Execution Core
The RC32334 integrates the RISCore32300, the same CPU core
found in the award-winning RC32364 microprocessor.
The RISCore32300 implements the Enhanced MIPS-II ISA. Thus, it
is upwardly compatible with applications written for a wide variety of
MIPS architecture processors, and it is kernel compatible with the
modern operating systems that support IDT’s 64-bit RISController
product family.
The RISCore32300 was explicitly defined and designed for inte-
grated processor products such as the RC32334. Key attributes of the
execution core found within this product include:
High-speed, 5-stage scalar pipeline executes to 150MHz. This
high performance enables the RC32334 to perform a variety of
performance intensive tasks, such as routing, DSP algorithms,
32-bit architecture with enhancements of key capabilities. Thus,
the RC32334 can execute existing 32-bit programs, while
enabling designers to take advantage of recent advances in
CPU architecture.
Count leading-zeroes/ones. These instructions are common to a
wide variety of tasks, including modem emulation, voice over IP
compression and decompression, etc.
Cache PREFetch instruction support, including a specialized
form intended to help memory coherency. System programmers
can allocate and stage the use of memory bandwidth to achieve
maximum performance.
8kB of 2-way set associative instruction cache
Programmable I/O
Local I/O
I/O Bus
32-bit, 66MHz PCI
Figure 2 RC32334 Based System Diagram
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Features Datasheet pdf IDTTM InterpriseTM Integrated Communicat ions Processor 79RC32334—Rev. Y RC3 2300 32-bit Microprocessor – Up to 15 0 MHz operation – Enhanced MIPS-II In struction Set Architecture (ISA) – Ca che prefetch instruction – Conditiona l move instruction – DSP instructions – Supports big or little endian oper ation – MMU with 32 page TLB – 8kB Instruction Cache, 2-way set associative – 2kB Data Cach e, 2-way set associative – Cache lock ing per line – Programmable on a page basis to implement a write-through no write allocate, write-through write all ocate, or write-back algorithms for cac he management – Compatible with a wid e variety of operating systems ◆ Loca l Bus Interface – Up to 75 MHz operat ion – 26-bit address bus – 32-bit d ata bus – Direct control of local mem ory and peripherals – Programmable sy stem watch-dog timers – Big or little endian support ◆ Interrupt Controlle r simplifies exception management ◆ Four general purpose 32-bit timer/counters ◆ Features Programmable .
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