79RC32334

IDTTM InterpriseTM Integrated Communications Processor 79RC32334—Rev. Y RC32300 32-bit Microprocessor – Up to 150 MHz operation – Enhanced MIPS-II Instruction Set Architecture (ISA) – Cache prefetch instruction – Conditional move instruction – DSP instructions – Supports big or little endian operation www.DataSheet4U.com – MMU with 32 page TLB – 8kB Instruction Cache, 2-way set associative – 2kB Data Cache, 2-way set associative – Cache locking per line – Programmable on a page basis to implement a write-through no write allocate, write-through write allocate, or write-back algorithms for cache management – Compatible with a wide variety of operating systems ◆ Local Bus Interface – Up to 75 MHz operation – 26-bit address bus – 32-bit data bus – Direct control of local memory and peripherals – Programmable system watch-dog timers – Big or little endian support ◆ Interrupt Controller simplifies exception management ◆ Four general purpose 32-bit timer/counters ◆ Features Programmable I/O (PIO) – Input/Output/Interrupt source – Individually programmable ◆ SDRAM Controller (32-bit memory only) – 4 banks, non-interleaved – Up to 512MB total SDRAM memory supported – Implements full, direct control of discrete, SODIMM, or DIMM memories – Supports 16Mb through 512Mb SDRAM device depths – Automatic refresh generation ◆ Serial Peripheral Interface (SPI) master mode interface ◆ UART Interface – Two 16550 compatible UARTs – Baud rate support up to 1.5 Mb/s – Modem control signals avai...