Document
512 K × 8 Static RAM
Features
■ High speed ❐ tAA = 17 ns
■ Low active power ❐ 1073 mW (max.)
■ Low CMOS standby power ❐ 2.75 mW (max.)
■ 2.0 V data retention (400 W at 2.0 V retention) ■ Automatic power-down when deselected ■ TTL-compatible inputs and outputs ■ Easy memory expansion with CE and OE features
Logic Block Diagram
CY7C1049BN
512 K × 8 Static RAM
Functional Description
The CY7C1049BN is a high-performance CMOS static RAM organized as 524,288 words by 8 bits. Easy memory expansion is provided by an active LOW Chip Enable (CE), an active LOW Output Enable (OE), and three-state drivers. Writing to the device is accomplished by taking Chip Enable (CE) and Write Enable (WE) inputs LOW. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A18). Reading from the device is accomplished by taking Chip Enable (CE) and Output Enable (OE) LOW while forcing Write Enable (WE) HIGH. Under these .