DSPIC30F202x

dsPIC30F1010/202X 28/44-Pin dsPIC30F1010/202X Enhanced Flash SMPS 16-Bit Digital Signal Controller Note: This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the “dsPIC30F Family Reference Manual” (DS70046). For more information on the device instruction set and programming, refer to the “dsPIC30F/ 33F Programmer’s Reference Manual” (DS70157). High-Performance Modified RISC CPU: Modified Harvard architecture C compiler optimized instruction set architecture 83 base instructions with flexible addressing modes 24-bit wide instructions, 16-bit wide data path 12 Kbytes on-chip Flash program space 512 bytes on-chip data RAM 16 x 16-bit working register array Up to 30 MIPS operation: - Dual Internal RC - 9.7 and 14.55 MHz (±1%) Industrial Temp - 6.4 and 9.7 MHz (±1%)...