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STPC Dataheets PDF



Part Number STPC
Manufacturers STMicroelectronics
Logo STMicroelectronics
Description X86 Core PC Compatible System-on-Chip
Datasheet STPC DatasheetSTPC Datasheet (PDF)

STPC® ATLAS X86 Core PC Compatible System-on-Chip for Terminals s s POWERFUL x86 PROCESSOR 64-BIT SDRAM UMA CONTROLLER GRAPHICS CONTROLLER - VGA & SVGA CRT CONTROLLER - 135MHz RAMDAC - ENHANCED 2D GRAPHICS ENGINE VIDEO INPUT PORT VIDEO PIPELINE - UP-SCALER - VIDEO COLOUR SPACE CONVERTER - CHROMA & COLOUR KEY SUPPORT TFT DISPLAY CONTROLLER PCI 2.1 MASTER / SLAVE / ARBITER ISA MASTER / SLAVE CONTROLLER 16-BIT LOCAL BUS INTERFACE PCMCIA INTERFACE CONTROLLER EIDE CONTROLLER 2 USB HOST HUB INTERFACE.

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STPC® ATLAS X86 Core PC Compatible System-on-Chip for Terminals s s POWERFUL x86 PROCESSOR 64-BIT SDRAM UMA CONTROLLER GRAPHICS CONTROLLER - VGA & SVGA CRT CONTROLLER - 135MHz RAMDAC - ENHANCED 2D GRAPHICS ENGINE VIDEO INPUT PORT VIDEO PIPELINE - UP-SCALER - VIDEO COLOUR SPACE CONVERTER - CHROMA & COLOUR KEY SUPPORT TFT DISPLAY CONTROLLER PCI 2.1 MASTER / SLAVE / ARBITER ISA MASTER / SLAVE CONTROLLER 16-BIT LOCAL BUS INTERFACE PCMCIA INTERFACE CONTROLLER EIDE CONTROLLER 2 USB HOST HUB INTERFACES I/O FEATURES - PC/AT+ KEYBOARD CONTROLLER - PS/2 MOUSE CONTROLLER - 2 SERIAL PORTS - 1 PARALLEL PORT - 16 GENERAL PURPOSE I/Os - I²C INTERFACE INTEGRATED PERIPHERAL CONTROLLER - DMA CONTROLLER - INTERRUPT CONTROLLER - TIMER / COUNTERS POWER MANAGEMENT UNIT WATCHDOG JTAG IEEE1149.1 SVGA CRTC www.DataSheet4U.com s ST PC At s s las PBGA516 s s s s s s s s Figure 0-1. Logic Diagram Host I/F x86 Core PCI m/s PCI Bus USB PMU wdog IPC ISA m/s PCI m/s I/Os IDE I/F ISA Bus PCMCIA s LB ctrl Local Bus Video Pipeline s s s C Key K Key LUT Monitor Cursor GE I/F VIP SDRAM CTRL TFT I/F TFT Video In Issue 1.0 - July 24, 2002 1/111 STPC® ATLAS DESCRIPTION The STPC Atlas integrates a standard 5th generation x86 core along with a powerful UMA graphics/video chipset, support logic including PCI, ISA, Local Bus, USB, EIDE controllers and combines them with standard I/O interfaces to provide a single PC compatible subsystem on a single device, suitable for all kinds of terminal and industrial appliances. s s s s s s s Fully www.DataSheet4U.com s s s s s s s s s s s s s s s s s s s s s s X86 Processor core static 32-bit 5-stage pipeline, x86 processor fully PC compatible. Can access up to 4GB of external memory. 8Kbyte unified instruction and data cache with write back and write through capability. Parallel processing integral floating point unit, with automatic power down. Runs up to 133 MHz (X2). Fully static design for dynamic clock control. Low power and system management modes. Optimized design for 2.5V operation. SDRAM Controller 64-bit data bus. Up to 90MHz SDRAM clock speed. Integrated system memory, graphic frame memory and video frame memory. Supports 8MB up to 128 MB system memory. Supports 16-Mbit, 64-Mbit and 128-Mbit SDRAMs. Supports 8, 16, 32, 64, and 128 MB DIMMs. Supports buffered, non buffered, and registered DIMMs 4-line write buffers for CPU to DRAM and PCI to DRAM cycles. 4-line read prefetch buffers for PCI masters. Programmable latency Programmable timing for SDRAM parameters. Supports -8, -10, -12, -13, -15 memory parts Supports memory hole between 1MB and 8MB for PCI/ISA busses. 32-bit access, Autoprecharge & Power-down are not supported. s s s s Enhanced 2D Graphics Controller Supports pixel depths of 8, 16, 24 and 32 bit. Full BitBLT implementation for all 256 raster operations defined for Windows. Supports 4 transparent BLT modes - Bitmap Transparency, Pattern Transparency, Source Transparency and Destination Transparency. Hardware clipping Fast line draw engine with anti-aliasing. Supports 4-bit alpha blended font for antialiased text display. Complete double buffered registers for pipelined operation. 64-bit wide pipelined architecture running at 90 MHz. Hardware clipping CRT Controller Integrated 135MHz triple RAMDAC allowing for 1280 x 1024 x 75Hz display. 8-, 16-, 24-bit pixels. Interlaced or non-interlaced output. Video Input port Accepts video inputs in CCIR 601/656 mode. Optional 2:1 decimator Stores captured video in off setting area of the onboard frame buffer. HSYNC and B/T generation or lock onto external video timing source. Video Pipeline Two-tap interpolative horizontal filter. Two-tap interpolative vertical filter. Color space conversion (RGB to YUV and YUV to RGB). Programmable window size. Chroma and color keying for integrated video overlay. s s s s s s s s s s s s s s s 2/111 Issue 1.0 - July 24, 2002 STPC® ATLAS TFT Interface Programmable panel size up to 1024 by 1024 pixels. Support for VGA and SVGA active matrix s TFT flat panels with 9, 12, 18-bit interface (1 pixel per clock). Support for XGA and SXGA active matrix s TFT flat panels with 2 x 9-bit interface (2 pixels per clock). Programmable image positionning. s Programmable blank space insertion in text s www.DataSheet4U.com mode. Programmable horizontal and vertical image s expansion in graphic mode. One fully programmable PWM (Pulse Width s Modulator) signals to adjust the flat panel brightness and contrast. Supports PanelLinkTM high speed serial s transmitter externally for high resolution panel interface. s s s s s s s s s s s s s s s s s s s s s s Local Bus interface Multiplexed with ISA/DMA interface. Low latency asynchronous bus 16-bit data bus with word steering capability. Programmable timing (Host clock granularity) 4 Programmable Flash Chip Select. 8 Programmable I/O Chip Select. I/O device timing (setup & recovery time) programmable Supports 32-bit Flash burst. 2-level hardware key pr.


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