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CY7C1470BV25 Dataheets PDF



Part Number CY7C1470BV25
Manufacturers Cypress Semiconductor
Logo Cypress Semiconductor
Description (CY7C147xBV25) 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM
Datasheet CY7C1470BV25 DatasheetCY7C1470BV25 Datasheet (PDF)

CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features ■ ■ Functional Description The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are equipped with the advanced.

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CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 72-Mbit (2M x 36/4M x 18/1M x 72) Pipelined SRAM with NoBL™ Architecture Features ■ ■ Functional Description The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are 2.5V, 2M x 36/4M x 18/1M x 72 synchronous pipelined burst SRAMs with No Bus Latency™ (NoBL™) logic, respectively. They are designed to support unlimited true back-to-back read or write operations with no wait states. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are equipped with the advanced (NoBL) logic required to enable consecutive read or write operations with data being transferred on every clock cycle. This feature dramatically improves the throughput of data in systems that require frequent read or write transitions. The CY7C1470BV25, CY7C1472BV25, and CY7C1474BV25 are pin-compatible and functionally equivalent to ZBT devices. All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. The clock input is qualified by the Clock Enable (CEN) signal, which when deasserted suspends operation and extends the previous clock cycle. Write operations are controlled by the Byte Write Selects (BWa–BWd for CY7C1470BV25, BWa–BWb for CY7C1472BV25, and BWa–BWh for CY7C1474BV25) and a Write Enable (WE) input. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Enables (CE1, CE2, CE3) and an asynchronous Output Enable (OE) provide for easy bank selection and output tri-state control. To avoid bus contention, the output drivers are synchronously tri-stated during the data portion of a write sequence. Pin-compatible and functionally equivalent to ZBT™ Supports 250 MHz bus operations with zero wait states ❐ Available speed grades are 250, 200, and 167 MHz Internally self-timed output buffer control to eliminate the need to use asynchronous OE Fully registered (inputs and outputs) for pipelined operation Byte Write capability Single 2.5V power supply 2.5V IO supply (VDDQ) Fast clock-to-output times ❐ 3.0 ns (for 250-MHz device) Clock Enable (CEN) pin to suspend operation Synchronous self-timed writes CY7C1470BV25, CY7C1472BV25 available in JEDEC-standard Pb-free 100-pin TQFP, Pb-free and non-Pb-free 165-ball FBGA package. CY7C1474BV25 available in Pb-free and non-Pb-free 209-ball FBGA package IEEE 1149.1 JTAG Boundary Scan compatible Burst capability—linear or interleaved burst order “ZZ” Sleep Mode option and Stop Clock option ■ ■ ■ ■ ■ ■ www.DataSheet4U.com ■ ■ ■ ■ ■ ■ Selection Guide Description Maximum Access Time Maximum Operating Current Maximum CMOS Standby Current 250 MHz 3.0 450 120 200 MHz 3.0 450 120 167 MHz 3.4 400 120 Unit ns mA mA Cypress Semiconductor Corporation Document #: 001-15032 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 29, 2008 [+] Feedback CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Logic Block Diagram – CY7C1470BV25 (2M x 36) A0, A1, A MODE CLK CEN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 www.DataSheet4U.com ADV/LD BW a BW b BW c BW d WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S E DQ s DQ Pa DQ Pb DQ Pc DQ Pd E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC SLEEP CONTROL Logic Block Diagram – CY7C1472BV25 (4M x 18) A0, A1, A MODE CLK CEN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 ADV/LD BW a BW b WE WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S DQ s DQ Pa DQ Pb E E INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC Sleep Control Document #: 001-15032 Rev. *D Page 2 of 29 [+] Feedback CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Logic Block Diagram – CY7C1474BV25 (1M x 72) A0, A1, A MODE CLK CEN ADDRESS REGISTER 0 A1 A1' D1 Q1 A0 A0' BURST D0 Q0 LOGIC ADV/LD C C WRITE ADDRESS REGISTER 1 WRITE ADDRESS REGISTER 2 www.DataSheet4U.com ADV/LD BW a BW b BW c BW d BW e BW f BW g BW h WRITE REGISTRY AND DATA COHERENCY CONTROL LOGIC WRITE DRIVERS MEMORY ARRAY S E N S E A M P S O U T P U T R E G I S T E R S D A T A S T E E R I N G O U T P U T B U F F E R S E E DQ s DQ Pa DQ Pb DQ Pc DQ Pd DQ Pe DQ Pf DQ Pg DQ Ph WE INPUT REGISTER 1 E INPUT REGISTER 0 E OE CE1 CE2 CE3 ZZ READ LOGIC Sleep Control Document #: 001-15032 Rev. *D Page 3 of 29 [+] Feedback CY7C1470BV25 CY7C1472BV25, CY7C1474BV25 Pin Configurations Figure 1. 100-Pin TQFP Pinout A A CE1 CE2 BWd BWc BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A A A CE1 CE2 NC NC BWb BWa CE3 VDD VSS CLK WE CEN OE ADV/LD A A NC NC N.


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