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PLL102-15 Dataheets PDF



Part Number PLL102-15
Manufacturers PhaseLink Corporation
Logo PhaseLink Corporation
Description Low Skew Output Buffer
Datasheet PLL102-15 DatasheetPLL102-15 Datasheet (PDF)

PLL102-15 Low Skew Output Buffer FEATURES Frequency range 25 ~ 60MHz. Internal phase locked loop will allow spread spec trum modulation on reference clock to pass to the outputs (up to 33kHz SST modulation). • Zero input - output delay. • Less than 700 ps device - device skew. • Less than 250 ps skew between outputs. www.DataSheet4U.com • Less than 200 ps cycle - cycle jitter. • Output Enable function tri -state outputs. • 3.3V operation. • Available in 8 -Pin 150mil SOIC. • • PIN CONFIGURATION.

  PLL102-15   PLL102-15


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