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PLL103-11 Dataheets PDF



Part Number PLL103-11
Manufacturers PhaseLink Corporation
Logo PhaseLink Corporation
Description Low Skew Buffers
Datasheet PLL103-11 DatasheetPLL103-11 Datasheet (PDF)

PLL103-11 Low Skew Buffers FEATURES Generates 13 copies of High-speed clock inputs. Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50% duty cycle with low jitter. • Less than 5ns delay. www.DataSheet4U.com • Skew between any outputs is less than 250 ps. • Tri-state pin for testing. • Frequency up to 150 MHz. • 3.0V-3.7V Supply range. • Available in 28-pin 300mil SOIC package. • • PIN CONFIGURATION VDD SDRAM0 SDRAM1 GND VDD SDRAM2.

  PLL103-11   PLL103-11


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PLL103-11 Low Skew Buffers FEATURES Generates 13 copies of High-speed clock inputs. Supports up to three SDRAM DIMMS synchronous clocks. • Supports 2-wire I2C serial bus interface with readback. • 50% duty cycle with low jitter. • Less than 5ns delay. www.DataSheet4U.com • Skew between any outputs is less than 250 ps. • Tri-state pin for testing. • Frequency up to 150 MHz. • 3.0V-3.7V Supply range. • Available in 28-pin 300mil SOIC package. • • PIN CONFIGURATION VDD SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 GND BUF_IN SDRAM4 SDRAM5 SDRAM12 VDD1 SDATA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD SDRAM11 SDRAM10 GND VDD SDRAM9 SDRAM8 GND VDD SDRAM7 SDRAM6 GND GND1 SCLK PLL103-11 BLOCK DIAGRAM SDRAM0 SDATA SCLK I2C Control SDRAM2 SDRAM3 SDRAM4 SDRAM5 SDRAM6 BUF_IN SDRAM7 SDRAM8 SDRAM9 SDRAM10 SDRAM11 SDRAM12 SDRAM1 POWER GROUP • • VDD: SDRAM (0:12) VDD1: I2C Circuitry GROUND GROUP • • GND: SDRAM (0:12) GND1: I2C Circuitry KEY SPECIFICATIONS • • • • BUF_IN to SDRAM outputs Delay: 1 ~ 5 ns. Output Slew: ≥ 1.5 V/ns. Output Skew: ± 250 ps. Output Duty Cycle: 50% ± 5%. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/07/00 Page 1 PLL103-11 Low Skew Buffers PIN DESCRIPTIONS Name SDRAM (0:5) SDRAM (6:11) SDRAM 12 www.DataSheet4U.com BUF_IN Number 2,3,6,7,10,11 18,19,22, 23,26,27 12 9 14 15 1,5,20,24,28 13 4,8,17,21,25 16 Type O O O I B I P P P P SDRAM Byte0 Clock outputs. SDRAM Byte1 Clock outputs. SDRAM Byte2 Clock outputs. Description Input for fanout buffers SDRAM (0:12). Serial data inputs for serial interface port. 3.3V Power supply for SDRAM buffer. 3.3V Power supply for I2C circuitry. Ground for SDRAM buffer. Power supply for I2C circuitry. SDATA SCLK VDD VDD1 GND GND1 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/07/00 Page 2 PLL103-11 Low Skew Buffers I2C BUS CONFIGURATION SETTING Address Assignment Slave Receiver/Transmitter Data Transfer Rate www.DataSheet4U.com A6 1 A5 1 A4 0 A3 1 A2 0 A1 0 A0 1 R/W _ Provides both slave write and readback functionality Standard mode at 100kbits/s This serial protocol is designed to allow both blocks write and read from the controller. The bytes must be accessed in sequential order from lowest to highest byte. Each byte transferred must be followed by 1 acknowledge bit. A byte transferred without acknowledged bit will terminate the transfer. The write or read block both begins with the master sending a slave address and a write condition (0xD2) or a read condition (0xD3). Following the acknowledge of this address byte, in Write Mode: the Command Byte and Byte Count Byte must be sent by the master but ignored by the slave, in Read Mode: the Byte Count Byte will be read by the master then all other Data Byte . Byte Count Byte default at power-up is = (0x09). Data Protocol I2C CONTROL REGISTERS 1. BYTE 0: SDRAM(0:5) Clock Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 11 10 7 6 3 2 Default 1 1 1 1 1 1 1 1 Description SDRAM5 (Active/Inactive) SDRAM4 (Active/Inactive) Reserved Reserved SDRAM3 (Active/Inactive) SDRAM2 (Active/Inactive) SDRAM1 (Active/Inactive) SDRAM0 (Active/Inactive) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/07/00 Page 3 PLL103-11 Low Skew Buffers 2. BYTE 1: SDRAM(6:11) Clock Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 www.DataSheet4U.com Bit 3 Pin# 27 26 23 22 19 18 Default 1 1 1 1 1 1 1 1 Description SDRAM11 (Active/Inactive) SDRAM10 (Active/Inactive) SDRAM9 (Active/Inactive) SDRAM8 (Active/Inactive) Reserved Reserved SDRAM7 (Active/Inactive) SDRAM6 (Active/Inactive) Bit 2 Bit 1 Bit 0 3. BYTE 2: SDRAM12 Clock Register (1=Enable, 0=Disable) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Pin# 12 - Default 1 1 1 1 1 1 1 1 Description Reserved SDRAM12 (Active/Inactive) Reserved Reserved Reserved Reserved Reserved Reserved 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 11/07/00 Page 4 PLL103-11 Low Skew Buffers ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS Supply Voltage Input Voltage, dc www.DataSheet4U.com Output Voltage, SYMBOL V DD VI VO TS TA MIN. V SS - 0.5 V SS - 0.5 V SS - 0.5 -65 0 MAX. 7.0 V DD + 0.5 V DD + 0.5 150 70 UNITS V V V °C °C dc Storage Temperature Ambient Operating Temperature Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC/DC Electrical Specifications PARAMETERS Input High Current Input Low Current Input High Voltage Input Low Voltage Input Frequency Input Capacitance SYMBOL I.


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