PLL130-69

PLL130-68/-69 High Speed Translator Buffers: Single ended to PECL or LVDS FEATURES Differential PECL (PLL130-68) or LVDS (PLL130-69) output. Accepts any single-ended REFIN input (with as low as 100mV swing). Internal AC coupling of REFIN Input range from 1.0MHz to 1.0 GHz. No Vref required. www.DataSheet4U.com No external current source required. 2.5 to 3.3V operation. Available in 3x3mm QFN. PIN CONFIGURATION (TOP VIEW) Q_bar VDD 13 NC REFIN NC NC 1 2 3 4 16 15 NC 14 Q 12 11 10 9 NC Q Q_bar OESEL PLL130-6x 5 6 7 8 GND NC DESCRIPTION The PLL130-68 and PLL130-69 are low cost, high performance, high speed, translator buffers that reproduce any input frequency from DC to 1.0GHz. They provide a pair of differential outputs (PECL for PLL130-68 or LVDS for PLL13069). Thanks to an internal AC coupling of the reference input (REFIN), any input signal with at least 100mV swing can be used as reference signal, regardless of its DC value. These chips are ideal for conversion from clipped sine wave, TTL, CMOS, or differential signal to LVDS or PECL. OUTPUT ENABLE LOGICAL LEVELS PLL130-68 OESEL 0 (Default) 1 OECTRL 0 (Default) 1 0 1 (Default) OUTPUT STATE Output enabled Tri-state Tri-state Output enabled OECTRL input: Logical states defined by PECL levels. PLL130-69 OESEL 0 (Default) 1 OECTRL 0 1 (Default) 0 (Default) 1 OUTPUT STATE Tri-state Output enabled Output enabled Tri-state OECTRL input: Logical states defined by CMOS levels. BLOCK DIAGRAM OECTRL ...