TTSV02622

Data Sheet June 2003 TTSV02622 STS-24 Backplane Transceiver Features s s s s Low-power 3.3 V supply. –40 °C to +125 °C industrial temperature range. 272-pin ball grid array (PBGA) package. www.DataSheet4U.com Allows wide range of applications for SONET network termination application as well as generic data moving for high-speed backplane data transfer. Clock/data recovery (CDR) function for high-speed serial backplane data transfer. CDR function uses Agere Systems Inc. proven 622 Mbits/s serial interface core. Two-channel CDR function provides 622 Mbits/s serial interface per channel for a total chip bandwidth of 1.24 Gbits/s (full duplex). Low-voltage differential signaling (LVDS) I/Os for CDR and reference clock signals. 8:1 data multiplexing/demultiplexing (MUX/ deMUX) for 77.76 MHz byte-wide data processing. CDR meets B jitter tolerance specification of ITU-T recommendation G.958. Powerdown option of CDR receiver on a perchannel basis. Pseudo-SONET protocol including A1/A2 framing. SONET scrambling and descrambling for required ones density (optional). Selected transport overhead (TOH) bytes insertion and detection for interdevice communication via the TOH serial link. Streamlined pointer processor (pointer mover) for 8 kHz frame alignment. FIFOs for alignment of incoming data to reference clock. FIFOs optionally align incoming data across all two channels for synchronous transport signal STS-24 operation (in dual STS-12 format). Independent data stream enables in ps...