DFPDIV

DFPDIV www.DataSheet4U.com Floating Point Pipelined Divider Unit ver 2.15 OVERVIEW ● Fully synthesizable, static synchronous design with no internal tri-states The DFPDIV uses the pipelined mathematics algorithm to divide two arguments. The input numbers format is according to IEEE754 standard. DFPDIV supports single precision real number. Divide operation was pipelined up to 15 levels. Input data are fed every clock cycle. The first result appears after 15 clock periods latency and next results are available each clock cycle. Full IEEE-754 precision and accuracy are included. DELIVERABLES ♦ Source code: VHDL Source Code or/and VERILOG Source Code or/and Encrypted, or plain text EDIF netlist VHDL & VERILOG test bench environment ◊ Active-HDL automatic simulation macros ◊ NCSim automatic simulation macros ◊ ModelSim automatic simulation macros ◊ Tests with reference responses Technical documentation ◊ Installation notes ◊ HDL core specification ◊ Datasheet Synthesis scripts Example application Technical support ◊ IP Core implementation support ◊ 3 months maintenance ◊ ◊ ◊ ● ● ● ♦ APPLICATION ● ● ● ● Math coprocessors DSP algorithms Embedded arithmetic coprocessor Data processing & control ♦ ♦ ♦ ♦ KEY FEATURES ● ● ● ● ● ● ● ● ● Full IEEE-754 compliance Single precision real format support Simple interface No programming required 15 levels pipeline Full accuracy and precision Results available at every clock Overflow, underflow and invalid operation flags Fully configurabl...