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CP8056 Dataheets PDF



Part Number CP8056
Manufacturers Chengpin
Logo Chengpin
Description EPROM/ROM-Based 8-Bit Microcontroller Series
Datasheet CP8056 DatasheetCP8056 Datasheet (PDF)

CHENGPIN Devices Included in this Data Sheet: • CP8056P : EPROM devices • CP8056P : Mask ROM devices CP8056 EPROM/ROM-Based 8-Bit Microcontroller Series www.DataSheet4U.com FEATURES • Only 42 single word instructions • All instructions are single cycle except for program branches which are two-cycle • 13-bit wide instructions • All ROM/EPROM area GOTO instruction • All ROM/EPROM area subroutine CALL instruction • 8-bit wide data path • 5-level deep hardware stack • Operating speed: DC-20 MHz.

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CHENGPIN Devices Included in this Data Sheet: • CP8056P : EPROM devices • CP8056P : Mask ROM devices CP8056 EPROM/ROM-Based 8-Bit Microcontroller Series www.DataSheet4U.com FEATURES • Only 42 single word instructions • All instructions are single cycle except for program branches which are two-cycle • 13-bit wide instructions • All ROM/EPROM area GOTO instruction • All ROM/EPROM area subroutine CALL instruction • 8-bit wide data path • 5-level deep hardware stack • Operating speed: DC-20 MHz clock input DC-100 ns instruction cycle Device CP8056 Pins # 18 I/O # 12 EPROM/ROM (Byte) 1K RAM (Byte) 49 • Direct, indirect addressing modes for data accessing • 8-bit real time clock/counter (Timer0) with 8-bit programmable prescaler • Internal Power-on Reset (POR) • Built-in Low Voltage Detector (LVD) for Brown-out Reset (BOR) • Power-up Reset Timer (PWRT) and Oscillator Start-up Timer(OST) • On chip Watchdog Timer (WDT) with internal oscillator for reliable operation and soft-ware watch-dog enable/disable control • Two I/O ports IOA and IOB with independent direction control • Soft-ware I/O pull-high/pull-down or open-drain control • One internal interrupt source: Timer0 overflow; Two external interrupt source: INT pin, Port B input change • Wake-up from SLEEP by INT pin or Port B input change • Power saving SLEEP mode • Programmable Code Protection • Selectable oscillator options: - RC: Resistor/Capacitor Oscillator - XT: Crystal/Resonator Oscillator - HF: High Frequency Crystal/Resonator Oscillator - LF: Low Frequency Crystal Oscillator • Wide-operating voltage range: - EPROM : 2.3V to 5.5V - ROM : 2.3V to 5.5V P.1/CP8056 CHENGPIN GENERAL DESCRIPTION CP8056 The CP8056 series is a family of low-cost, high speed, high noise immunity, EPROM/ROM-based 8-bit CMOS microcontrollers. It employs a RISC architecture with only 42 instructions. All instructions are single cycle except for program branches which take two cycles. The easy to use and easy to remember instruction set reduces development time significantly. The CP8056 series consists of Power-on Reset (POR), Brown-out Reset (BOR), Power-up Reset Timer (PWRT), Oscillator Start-up Timer(OST), Watchdog Timer, EPROM/ROM, SRAM, tri-state I/O port, I/O pull-high/open-drain/pull-down control, Power saving SLEEP mode, real time programmable clock/counter, www.DataSheet4U.com Interrupt, Wake-up from SLEEP mode, and Code Protection for EPROM products. There are four oscillator configurations to choose from, including the power-saving LP (Low Power) oscillator and cost saving RC oscillator. The CP8056 address 1K×13 of program memory. The CP8056 can directly or indirectly address its register files and data memory. All special function registers including the program counter are mapped in the data memory. BLOCK DIAGRAM Oscillator Circuit 5-level STACK Watchdog Timer Program Counter FSR SRAM ALU EPROM / ROM Instruction Decoder PORTA PORTB Interrupt Control Timer0 Accumulator P.2/CP8056 CHENGPIN PIN CONNECTION PDIP, SOP IOA2 IOA3 T0CKI RSTB 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 IOA1 IOA0 OSCI OSCO Vdd IOB7 IOB6 IOB5 IOB4 CP8056 SSOP, TSSOP IOA2 IOA3 T0CKI RSTB Vss Vss IOB0/INT IOB1 IOB2 IOB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 14 13 12 11 IOA1 IOA0 OSCI OSCO Vdd IOB7 IOB6 IOB5 IOB4 www.DataSheet4U.com Vss IOB0/INT IOB1 IOB2 IOB3 CP8056P/56S CP8056SS/TS 15 Vdd PIN DESCRIPTIONS Description IOA0 ~ IOA3 as bi-direction I/O port Bi-direction I/O pin with system wake-up function / External interrupt input Bi-direction I/O port with system wake-up function Clock input to Timer0. Must be tied to Vss or Vdd, if not in use, to reduce current T0CKI I consumption RSTB I System clear (RESET) input. This pin is an active low RESET to the device. X’tal type: Oscillator crystal input OSCI I RC type: Clock input of RC oscillator X’tal type: Oscillator crystal output. OSCO O RC mode: Outputs with the instruction cycle rate Vdd Positive supply Vss Ground Legend: I=input, O=output, I/O=input/output Name IOA0 ~ IOA3 IOB0/INT IOB1 ~ IOB7 I/O I/O I/O I/O P.3/CP8056 CHENGPIN 1.0 MEMORY ORGANIZATION CP8056 memory is organized into program memory and data memory. 1.1 Program Memory Organization CP8056 The CP8056 have a 10-bit Program Counter capable of addressing a 1K×13 program memory space. The RESET vector for the CP8056 is at 3FFh. The H/W interrupt vector is at 008h. And the S/W interrupt vector is at 002h. www.DataSheet4U.com CP8056 supports all ROM/EPROM area CALL/GOTO instructions without page. FIGURE 1.1: Program Memory Map and STACK PC<9:0> Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 3FFh Reset Vector : : 008h H/W Interrupt Vector 002h S/W Interrupt Vector 000h CP8056 P.4/CP8056 CHENGPIN CP8056 1.2 Data Memory Organization Data memory is composed of Special Function Registers and General Purpose Registers. The General Purpose Registers are accessed either directly or indirectly through the FSR register. The Special Function Registers are register.


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