IDT74ALVCH16260

IDT74ALVCH16260 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 12-BIT TO 24-BIT MULTIPLEXED D-TYPE LATCH WITH 3-STATE OUTPUTS AND BUS-HOLD 0.5 MICRON CMOS Technology Typical tSK(o) (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) VCC = 3.3V ± 0.3V, Normal Range VCC = 2.7V to 3.6V, Extended Range www.DataSheet4U.com VCC = 2.5V ± 0.2V CMOS power levels (0.4µ W typ. static) Rail-to-Rail output swing for increased noise margin Available in SSOP and TSSOP packages IDT74ALVCH16260 FEATURES: DESCRIPTION: DRIVE FEATURES: High Output Drivers: ±24mA Suitable for heavy loads APPLICATIONS: 3.3V high speed systems 3.3V and lower voltage computing systems This 12-bit to 24-bit multiplexed D-type latch is built using advanced dual metal CMOS technology. The ALVCH16260 is used in applications in which two separate data paths must be multiplexed onto, or demultiplexed from, a single data path. Typical applications include multiplexing and/or demultiplexing address and data information in microprocessor or bus-interface applications. This device also is useful in memory interleaving applications. Three 12-bit I/O ports (A1-A12, 1B1-1B12, and 2B1-2B12) are available for address and/or data transfer. The output-enable (OE1B, OE2B, and OEA) inputs control the bus transceiver functions. The OE1B and OE2B control signals also allow bank control in the A-to-B di...