ADPCM Processor. AT2004 Datasheet


AT2004 Processor. Datasheet pdf. Equivalent


AT2004


4 Channels ADPCM Processor
AT2004 4 Channels ADPCM Processor with Echo Cancellation and Conferencing

Atelic Systems, Inc.
AT2004 Application Note Preliminary 4 Channels ADPCM Processor with Echo Cancellation and Conferencing Version 1.0 January 29, 2001 Description
www.DataSheet4U.com follows the G.726

The AT2004 is a four full-duplex channels, ADPCM processor with conferencing and echo cancellation capabilities. It ITU Standard for ADPCM compression for 40k, 32k, 24k and 16k bitrates with selectable µ-law and Alaw input/output. It conforms to ITU G.165/G.168 Digital Adaptive Echo Canceller specification for line echo delay up to 20ms. Using the command serial interface, each individual half-channel can be independently configured for ADPCM, conferencing and echo canceling features.

Features
• • • • • • • • • 4 full channels of ITU G.726 ADPCM 4 full channels of ITU G.165/G.168 complia nt echo cancellation with up to 20ms echo delay Fast and robust convergence for adaptive echo canceller, even in the presence of background noise Nonlinear processing with adaptive suppression threshold and comfort noise generation for echo canceller Per channel selectable µ-Law and A-law input/output On-chip time slot assignment Available internal clock generator and frame sync. generator Simple 3-wire serial command port for chip configuration Conferencing capabilities for up to 3 additional sound sources

Application...



AT2004
AT2004
4 Channels ADPCM Processor with Echo Cancellation and Conferencing
Atelic Systems, Inc.
Description
AT2004 Application Note Preliminary
4 Channels ADPCM Processor with Echo Cancellation and Conferencing
Version 1.0 January 29, 2001
The AT2004 is a four full-duplex channels, ADPCM processor with conferencing and echo cancellation capabilities. It
www.DaftaoSllhoewets4Uth.ceomG.726 ITU Standard for ADPCM compression for 40k, 32k, 24k and 16k bitrates with selectable µ-law and A-
law input/output. It conforms to ITU G.165/G.168 Digital Adaptive Echo Canceller specification for line echo delay up to
20ms. Using the command serial interface, each individual half-channel can be independently configured for ADPCM,
conferencing and echo canceling features.
Features
4 full channels of ITU G.726 ADPCM
4 full channels of ITU G.165/G.168 complia nt echo cancellation with up to 20ms echo delay
Fast and robust convergence for adaptive echo canceller, even in the presence of background noise
Nonlinear processing with adaptive suppression threshold and comfort noise generation for echo canceller
Per channel selectable µ-Law and A-law input/output
On-chip time slot assignment
Available internal clock generator and frame sync. generator
Simple 3-wire serial command port for chip configuration
Conferencing capabilities for up to 3 additional sound sources
Applications
DECT
VoIP / VoDSL
Wireless telephone systems
Wireless PBX systems
Default Settings
4 channels of µ-law PCM input on Xin in time slot 0, 1, 2, 3
4 channels of the corresponding ADPCM output at 32kbps on Xout in time slot 0, 1, 2, 3
4 channels of ADPCM input at 32kbps on Yin in time slot 0, 1, 2, 3
4 channels of corresponding PCM µ-law output on Yout in time slot 0, 1, 2, 3
Echo cancellation enabled for four channels
Conferencing disabled
Note: To change the default settings, commands could be sent through the 3-wire interface.
Page 1 of 25
©2001 Atelic System, Inc

AT2004
PIN Description
AT2004
4 Channels ADPCM Processor with Echo Cancellation and Conferencing
PIN SYMBOL
16 XIN
20 XOUT
27
www.DataSheet4U.com25
YIN
FSY
24 YOUT
2 RSTZ
13 XTAL1/MCLK
12 XTAL2
17 CLKP
26 CLKA
18 SYNC1
15 SYNC2
11 SYNC3
10 SYNC4
4 TM1
3 TM0
7 A1
6 A0
22 SDI/SDO
21 SCLK
23 SCSZ
28 VDD
14 Vss1
19 Vss2
TYPE
I
O
I
I/O
O
I
I
O
I/O
I/O
O
O
O
O
I
I
I
I
I/O
I
I
-
-
-
DESCRIPTION
X Channel Data In. Sampled on the falling edge of CLKP during
selected time slots with MSB first.
X Channel Data Out. Updated on the rising edge of CLKP during
selected time slots with MSB first.
Y Channel Data In. Sampled on the falling edge of CLKA during
selected time slots with MSB first.
Y Channel Frame Sync. Master Y Channel Frame Sync. Signal
followed by the first time slot of transmission. It can be either
input or output by initial setup sequence.
Y Channel Data Out. Updated on the rising edge of CLKA
during selected time slots with MSB first.
Reset. Low active signal to force chip reset.
Crystal In & Out. 14.318 MHz Crystal connected∗∗∗.
PCM Clock. It can be either input created by external control
circuit, or output generated by internal control circuit.
ADPCM Clock. It can be either input created by external control
circuit, or output generated by internal control circuit.
Sync 1. Frame sync. for 1st CODEC.
Sync 2. Frame sync. for 2nd CODEC.
Sync 3. Frame sync. for 3rd CODEC.
Sync 4. Frame sync. for 4th CODEC.
TM1 &TM0 . Tie to Ground for normal operation.
A1 & A0. Address ID key for 3-wire serial port. If match, 3-wire
serial port can be enabled for configuration.
Serial Data In. Data for configuration on the fly by 3-wire serial
port. Sampled on the rising edge of SCLK with LSB first.
Serial Data Out. Output data after sending Read Memory
command by 3-wire serial port. Sampled on the rising edge of
SCLK with LSB first.
Serial Clock. Used to write to the 3-wire serial port registers or
output data from 3-wire serial port registers.
Serial Port Chip Select. Low active to enable 3-wire serial port.
Power. 3.3 Volts.
Ground. 0 Volt.
∗∗∗For clock source other than 14.318MHz, please contact Atelic Systems.
Page 2 of 25
©2001 Atelic System, Inc




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