WCSS0232V1P

WCSS0232V1P Revised: February 7, 2002 WCSS0232V1P 64K x 32 Synchronous-Pipelined Cache RAM Features Supports 133-MHz bus for Pentium® and PowerPC™ operations with zero wait states Fully registered inputs and outputs for pipelined operation 64K x 32 common I/O architecture Single 3.3V power supply Fast clock-to-output times www.DataSheet4U.com All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns (133-MHz device). The WCSS0232V1P supports either the interleaved burst sequence used by the Intel Pentium processor or a linear burst sequence used by processors such as the PowerPC. The burst sequence is selected through the MODE pin. Accesses can be initiated by asserting either the Processor Address Strobe (ADSP) or the Controller Address Strobe (ADSC) at clock rise. Address advancement through the burst sequence is controlled by the ADV input. A 2-bit on-chip wraparound burst counter captures the first address in a burst sequence and automatically increments the address for the rest of the burst access. Byte write operations are qualified with the four Byte Write Select (BW[3:0]) inputs. A Global Write Enable (GW) overrides all byte write inputs and writes data to all four bytes. All writes are conducted with on-chip synchronous self-timed write circuitry. Three synchronous Chip Select...