WCSS0418V1F

Y7C1032 WCSS0418V1F 256K x 18 Synchronous 3.3V Cache RAM Features Supports 117-MHz microprocessor cache systems with zero wait states 256K by 18 common I/O Fast clock-to-output times — 7.5 ns (117-MHz version) Two-bit wrap-around counter supporting either interleaved or linear burst sequence www.DataSheet4U.com Separate processor and controller address strobes provide direct interface with the processor and external cache controller Synchronous self-timed write Asynchronous output enable I/Os capable of 2.5–3.3V operation JEDEC-standard pinout 100-pin TQFP packaging ZZ “sleep” mode Functional Description The WCSS0418V1F is a 3.3V, 256K by 18 synchronous cache RAM designed to interface with high-speed microprocessors with minimum glue logic. Maximum access delay from clock rise is 7.5 ns (117-MHz version). A 2-bit on-chip counter captures the first address in a burst and increments the address automatically for the rest of the burst access. The allows WCSS0418V1F both interleaved or linear burst sequences, selected by the MODE input pin. A HIGH selects an interleaved burst sequence, while a LOW selects a linear burst sequence. Burst accesses can be initiated with the Processor Address Strobe (ADSP) or the Cache Controller Address Strobe (ADSC) inputs. Address advancement is controlled by the Address Advancement (ADV) input. A synchronous self-timed write mechanism is provided to simplify the write interface. A synchronous chip enable input and an async...