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AS7C251MNTD32A Dataheets PDF



Part Number AS7C251MNTD32A
Manufacturers Alliance Semiconductor Corporation
Logo Alliance Semiconductor Corporation
Description (AS7C251MNTD32A / AS7C251MNTD36A) 2.5V 1M x 32/36 Pipelined SRAM
Datasheet AS7C251MNTD32A DatasheetAS7C251MNTD32A Datasheet (PDF)

January 2005 ® AS7C251MNTD32A AS7C251MNTD36A 2.5V 1M × 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns • Fast OE access time: 3.2/3.5/3.8 ns • Fully synchronous operation • pipelined mode www.DataSheet4U.com • Common data inputs and data outputs • Asynchronous output enable control Logic block diagram A[19:0] 20 D • Available in 100.

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January 2005 ® AS7C251MNTD32A AS7C251MNTD36A 2.5V 1M × 32/36 Pipelined SRAM with NTDTM Features • Organization: 1,048,576 words × 32 or 36 bits • NTD™architecture for efficient bus operation • Fast clock speeds to 200 MHz • Fast clock to data access: 3.2/3.5/3.8 ns • Fast OE access time: 3.2/3.5/3.8 ns • Fully synchronous operation • pipelined mode www.DataSheet4U.com • Common data inputs and data outputs • Asynchronous output enable control Logic block diagram A[19:0] 20 D • Available in 100-pin TQFP packages • Byte write enables • Clock enable for operation hold • Multiple chip enables for easy expansion • 2.5V core power supply • Self-timed write cycles • Interleaved or linear burst modes • Snooze mode for standby operation Address register Burst logic Q 20 CLK CE0 CE1 CE2 R/W BWa BWb BWc BWd ADV / LD LBO ZZ D Q 20 Write delay addr. registers CLK Control logic CLK Write Buffer CLK 1M x 32/36 SRAM Array DQ[a,b,c,d] 32/36 D Data Q Input Register CLK 32/36 32/36 32/36 32/36 CLK CEN CLK OE Output Register 32/36 OE DQ[a,b,c,d] Selection guide -200 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 1/17/05, V 1.2 -166 6 166 3.5 400 150 90 -133 7.5 133 3.8 350 140 90 Units ns MHz ns mA mA mA P. 1 of 18 5 200 3.2 450 170 90 Alliance Semiconductor Copyright © Alliance Semiconductor. All rights reserved. AS7C251MNTD32A AS7C251MNTD36A ® 2.5V 32 Mb Synchronous SRAM products list1,2 Org 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 www.DataSheet4U.com 1MX36 2MX18 1MX32 1MX36 2MX18 1MX32 1MX36 Part Number AS7C252MPFS18A AS7C251MPFS32A AS7C251MPFS36A AS7C252MPFD18A AS7C251MPFD32A AS7C251MPFD36A AS7C252MFT18A AS7C251MFT32A AS7C251MFT36A AS7C252MNTD18A AS7C251MNTD32A AS7C251MNTD36A AS7C252MNTF18A AS7C251MNTF32A AS7C251MNTF36A Mode PL-SCD PL-SCD PL-SCD PL-DCD PL-DCD PL-DCD FT FT FT NTD-PL NTD-PL NTD-PL NTD-FT NTD-FT NTD-FT Speed 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 200/166/133 MHz 200/166/133 MHz 200/166/133 MHz 7.5/8.5/10 ns 7.5/8.5/10 ns 7.5/8.5/10 ns 1 Core Power Supply: VDD = 2.5V + 0.125V 2 I/O Supply Voltage: VDDQ = 2.5V + 0.125V PL-SCD PL-DCD FT NTD1-PL NTD-FT : : : : : Pipelined Burst Synchronous SRAM - Single Cycle Deselect Pipelined Burst Synchronous SRAM - Double Cycle Deselect Flow-through Burst Synchronous SRAM Pipelined Burst Synchronous SRAM with NTDTM Flow-through Burst Synchronous SRAM with NTDTM 1. NTD: No Turnaround Delay. NTDTM is a trademark of Alliance Semiconductor Corporation. All trademarks mentioned in this document are the property of their respective owners. 1/17/05, V 1.2 Alliance Semiconductor P. 2 of 18 AS7C251MNTD32A AS7C251MNTD36A ® Pin assignment 100-pin TQFP - top view A A CE0 CE1 BWd BWc BWb BWa CE2 VDD VSS CLK R/W CEN OE ADV/LD A A A A 100 99 98 97 96 95 94 93 www.DataSheet4U.com NC/DQPc DQc0 DQc1 VDDQ VSSQ DQc2 DQc3 DQc4 DQc5 VSSQ VDDQ DQc6 DQc7 VDD VDD NC VSS DQd0 DQd1 VDDQ VSSQ DQd2 DQd3 DQd4 DQd5 VSSQ VDDQ DQd6 DQd7 NC/DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 92 91 90 89 88 87 86 85 84 83 82 81 TQFP 14 x 20mm 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb/NC DQb7 DQb6 VDDQ VSSQ DQb5 DQb4 DQb3 DQb2 VSSQ VDDQ DQb1 DQb0 VSS NC VDD ZZ DQa7 DQa6 VDDQ VSSQ DQa5 DQa4 DQa3 DQa2 VSSQ VDDQ DQa1 DQa0 DQPa/NC Note: For pins 1, 30, 51, and 80, NC applies to the x32 configuration. DQPn applies to the x36 configuration. 1/17/05, V 1.2 LBO A A A A A1 A0 NC NC VSS VDD NC A A A A A A A A 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Alliance Semiconductor P. 3 of 18 AS7C251MNTD32A AS7C251MNTD36A ® Functional description The AS7C251MNTD32A/36A family is a high performance CMOS 32 Mbit synchronous Static Random Access Memory (SRAM) organized as 1,048,576 words × 32 or 36 bits and incorporates a LATE LATE Write. This variation of the 32Mb+ synchronous SRAM uses the No Turnaround Delay (NTD™) architecture, featuring an enhanced write operation that improves bandwidth over pipelined burst devices. In a normal pipelined burst device, the write data, command, and address are all applied to the device on the same clock edge. If a read command follows this write command, the system must wait for two 'dead' cycles for valid data to become available. These dead cycles can significantly reduce overall bandwidth for applications requiring random access or read-modify-write operations. NTD™ devices use the memory bus more efficiently by introducing a write latency which matches the two-cycle pipelined or one-cycle flow-through read latency. Write data is applied two cycles after the write command and address, allowing the read pipeline to clear. With NTD™, write and read operations can be used in any order without producing dead bus cycles. www.DataSh.


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