AS7C251MPFS18A

December 2004 ® AS7C251MPFS18A 2.5V 1M x 18 pipelined burst synchronous SRAM Features Organization: 1,048,576 x18 bits Fast clock speeds to 166 MHz Fast clock to data access: 3.5/3.8 ns Fast OE access time: 3.5/3.8 ns Fully synchronous register-to-register operation Single-cycle deselect Asynchronous output enable control Available 100-pin TQFP package Individual byte write and global write Multiple chip enables for easy expansion 2.5V core power supply Linear or interleaved burst control Snooze mode for reduced power-standby Common data inputs and data outputs www.DataSheet4U.com Logic block diagram LBO CLK ADV ADSC ADSP A[19:0] CLK CS CLR Burst logic 20 18 20 20 Q D CS Address 1M x 18 Memory array 18 18 register CLK GWE BWb BWE BWa CE0 CE1 CE2 D DQb Q CLK D DQa Q Byte Write registers Byte Write registers CLK D 2 OE CE CLK D ZZ Enable register Q Output registers CLK Input registers CLK Power down Enable delay register Q CLK OE 18 DQ[a,b] Selection guide -166 Minimum cycle time Maximum clock frequency Maximum clock access time Maximum operating current Maximum standby current Maximum CMOS standby current (DC) 6 166 3.5 290 85 40 -133 7.5 133 3.8 270 75 40 Units ns MHz ns mA mA mA 12/23/04, v. 2.2 Alliance Semiconductor 1 of 19 Copyright © Alliance Semiconductor. All rights reserved. AS7C251MPFS18A ® 16 Mb 2.5V Synchronous SRAM products list1,2 Org 1MX18 512KX32 512KX36 1MX18 512KX32 512KX36 1MX18 512KX32 www.DataShe...