August 2004 rev 2.0 DDR 13-Bit to 26-Bit Registered Buffer
ASM4SSTVF16859
off. Note that RESETB should be supported with a
Features
Differential clock signals. Meets SSTL_2 class II specifications on outputs.
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LVCMOS level at a valid state since VREF may not be stable during power-up.
To ensure that outputs are at a defined logi...
