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UT54ACTS191 Dataheets PDF



Part Number UT54ACTS191
Manufacturers ETC
Logo ETC
Description Synchronous 4-Bit Up-Down Binary Counters
Datasheet UT54ACTS191 DatasheetUT54ACTS191 Datasheet (PDF)

UT54ACS191/UT54ACTS191 Radiation-Hardened Synchronous 4-Bit Up-Down Binary Counters FEATURES Single down/up count control line counters Fully synchronous in count modes Asynchronously presetable with load control www.DataSheet4U.com radiation-hardened CMOS High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS191 and the UT54ACTS191 are synchronous 4bit reversible up-down binary counters. Sync.

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UT54ACS191/UT54ACTS191 Radiation-Hardened Synchronous 4-Bit Up-Down Binary Counters FEATURES Single down/up count control line counters Fully synchronous in count modes Asynchronously presetable with load control www.DataSheet4U.com radiation-hardened CMOS High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack DESCRIPTION The UT54ACS191 and the UT54ACTS191 are synchronous 4bit reversible up-down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed. Synchronous operation eliminates the output counting spikes associated with asynchronous counters. The outputs of the four flip-flops are triggered on a low-to-highlevel transition of the clock input if the enable input (CTEN) is low. A logic one applied to CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up and when D/U is high, it counts down. The counters feature a fully independent clock circuit. Changes at control inputs (CTEN and D/U) that will modify the operating mode have no effect on the contents of the counter until clocking occurs. The counters are fully programmable. The outputs may be preset to either logic level by placing a low on the load input and entering the desired data at the data inputs. The output will change to agree with the data inputs independently of the level of the clock input. The asynchronous load allows counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. Two outputs have been made available to perform the cascading function: ripple clock and maximum/minimum (MAX/MIN) count. The MAX/MIN output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is zero (all outputs low) counting down or maximum (15) counting up. 123 PINOUTS 16-Pin DIP Top View B B A 1 15 3 13 V A RCO LOAD 10 9 C D/ Q Q SS 5 6 16-Lead Flatpack Top View 16 Q Q CTEN U C D SS DD 2 14 4 12 11 7 9 C MAX/MIN CLK The ripple clock output (RCO) produces a low-level output pulse under those same conditions but only while the clock input is low. The counters easily cascade by feeding the RCO to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. Use the MAX/MIN count output to accomplish look-ahead for highspeed operation. The devices are characterized over full military temperature range of -55 C to +125 Rad-Hard MSI Logic UT54ACS191/UT54ACTS191 FUNCTION TABLE FUNCTION Count Up Count Down Asynchronous Reset No Change LOAD H H L H CTEN L L X H D/U L H X X X X CLK (11) LOAD (15) A B C D (1) (10) (9) 5D (1) (2) (4) (8) 7 CLK CTEN D/U LOGIC SYMBOL (4) (5) (14) CTRDIV 16 G1 M2 (DWN) 2(CT=0)Z6 M3 (UP) 3(CT=9)Z6 1,2 -/1,3+ G4 6,1,4 C5 (12) MAX/MIN (13) RCO (3) (2) (6) (7) QA QB QC QD www.DataSheet4U.com Note: 1. Logic symbol in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12. LOGIC DIAGRAM CLK (14) (13) (12) RCO D/U (5) MAX/MIN A (15) 1J S Q C1 1K R Q (3) QA CTEN (4) B (1) 1J S Q C1 Q 1K R (2) QB C (10) 1J S Q C1 Q 1K R (6) QC D (9) 1J S Q C1 Q 1K R (7) Q D LOAD (11) Rad-Hard MSI Logic 124 UT54ACS191/UT54ACTS191 RADIATION HARDNESS SPECIFICATIONS 1 PARAMETER Total Dose SEU Threshold 2 SEL Threshold Neutron Fluence LIMIT 1.0E6 80 120 1.0E14 UNITS rads(Si) MeV-cm2/mg MeV-cm2/mg n/cm2 Notes: 1. Logic will not latchup during radiation exposure within the limits defined in the table. 2. Device storage elements are immune to SEU affects. www.DataSheet4U.com ABSOLUTE MAXIMUM RATINGS PARAMETER Supply voltage Voltage any pin Storage Temperature range Maximum junction temperature Lead temperature (soldering 5 seconds) Thermal resistance junction to case DC input current Maximum power dissipation LIMIT -0.3 to 7.0 -.3 to VDD +.3 -65 to +150 +175 +300 20 10 1 UNITS V V C C C C/W mA W SYMBOL VDD VI/O TSTG TJ TLS JC II PD Note: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS SYMBOL VDD VIN TC PARAMETER Supply voltage Input voltage any pin Temperature range LIMIT 4.5 to 5.5 0 to VDD -55 to + 125 UNITS V V C 125 Rad-Hard MSI Logic UT54ACS191/UT54ACTS191 DC ELECTRICAL CHARACTERISTICS 7 (VDD = 5.0V 10%; VSS = 0V 6, -55 C < TC < +125 C) SYMBOL VIL PARAMETER Low-level input voltage 1 ACTS ACS High-level input voltage 1 ACTS ACS Input leakage current ACTS/ACS Low-level output voltage 3 ACTS ACS High-.


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