PLL Clock Driver
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Description
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PI6CV857L
PLL Clock Driver for 2.5V DDR-SDRAM Memory
Product Features
PLL clock distribution optimized for Double Data Rate SDRAM applications. Distributes one differential clock input pair to ten differential clock output pairs. Inputs (CLK,CLK) and (FBIN,FBIN): SSTL_2 Input PWRDWN: LVCMOS www.DataSheet4U.com Outputs (Yx, Yx), (FBOUT, FBOUT): SSTL_2 External feedback pins (FBIN,FBIN) are used to synchronize the outputs to the clock input. Operates at AVDD = 2.5V for core circuit and internal PLL, and VDDQ = 2.5V for differential output drivers Available Packages: Plastic 48-pin TSSOP
Product Description
PI6CV857L PLL clock device is developed for registered DDR DIMM applications This PLL Clock Buffer is designed for 2.5 VDDQ and 2.5V AVDD operation and differential data input and output levels. Package options include plastic Thin Shrink Small-Outline Package (TSSOP).The device is a zero delay buffer that distributes a differential clock input pair (CLK, CLK) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (FBOUT,FBOUT) . The clock outputs are controlled by the input clocks (CLK, CLK), the feedback clocks (FBIN,FBIN), t...
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