ADN2811 IC Datasheet

ADN2811 Datasheet PDF, Equivalent


Part Number

ADN2811

Description

OC-48/OC-48 FEC Clock and Data Recovery IC

Manufacture

Analog Devices

Total Page 16 Pages
PDF Download
Download ADN2811 Datasheet PDF


ADN2811
a OC-48/OC-48 FEC Clock and Data Recovery IC
with Integrated Limiting Amp
ADN2811
FEATURES
Meets SONET Requirements for Jitter Transfer/
Generation/Tolerance
Quantizer Sensitivity: 4 mV Typ
Adjustable Slice Level: ؎100 mV
1.9 GHz Minimum Bandwidth
Patented Clock Recovery Architecture
Loss of Signal Detect Range: 3 mV to 15 mV
www.DataSheet4US.cionmgle Reference Clock Frequency for Both Native
SONET and 15/14 (7%) Wrapper Rate
Choice of 19.44 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz
REFCLK LVPECL/LVDS/LVCMOS/LVTTL
Compatible Inputs (LVPECL/LVDS Only at 155.52 MHz)
19.44 MHz Oscillator On-Chip to Be Used with
External Crystal
Loss of Lock Indicator
Loopback Mode for High Speed Test Data
Output Squelch and Bypass Features
Single-Supply Operation: 3.3 V
Low Power: 540 mW Typical
7 mm ؋ 7 mm 48-Lead LFCSP
APPLICATIONS
SONET OC-48, SDH STM-16, and 15/14 FEC
WDM Transponders
Regenerators/Repeaters
Test Equipment
Backplane Applications
PRODUCT DESCRIPTION
The ADN2811 provides the receiver functions of quantization,
signal level detect, and clock and data recovery at OC-48 and
OC-48 FEC rates. All SONET jitter requirements are met,
including jitter transfer, jitter generation, and jitter tolerance.
All specifications are quoted for –40؇C to +85؇C ambient
temperature, unless otherwise noted.
The device is intended for WDM system applications and can
be used with either an external reference clock or an on-chip
oscillator with external crystal. Both the 2.48 Gb/s and 2.66 Gb/s
digital wrapper rate is supported by the ADN2811, without any
change of reference clock.
This device, together with a PIN diode and a TIA preamplifier,
can implement a highly integrated, low cost, low power, fiber
optic receiver.
The receiver front end signal detect circuit indicates when the
input signal level has fallen below a user-adjustable threshold.
The signal detect circuit has hysteresis to prevent chatter at
the output.
The ADN2811 is available in a compact 7 mm × 7 mm 48-lead
chip scale package.
FUNCTIONAL BLOCK DIAGRAM
SLICEP/N
VCC VEE
2 ADN2811
PIN
QUANTIZER
NIN
PHASE
SHIFTER
PHASE
DET.
LOOP
FILTER
CF1 CF2
LOL
LOOP
FILTER
VCO
FREQUENCY
LOCK
DETECTOR
VREF
LEVEL
DETECT
THRADJ SDOUT
DATA
RETIMING
2
DATAOUTP/N
2
CLKOUTP/N
FRACTIONAL
DIVIDER
RATE
2
2
/n
XTAL
OSC
REFSEL[0..1]
REFCLKP/N
XO1
XO2
REFSEL
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2002 Analog Devices, Inc. All rights reserved.

ADN2811
ADN2811–SPECIFICATIONS (TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 4.7 F, SLICEP = SLICEN = VCC,
unless otherwise noted.)
Parameter
Conditions
Min
QUANTIZER–DC CHARACTERISTICS
Input Voltage Range
@ PIN or NIN, DC-Coupled
Peak-to-Peak Differential Input
Input Common-Mode Level
DC-Coupled. (See Figure 22)
Differential Input Sensitivity
PIN–NIN, AC-Coupled1, BER = 1 ؋ 10–10
Input Overdrive
Figure 4
Input Offset
Input rms Noise
BER = 1 ؋ 10–10
0
0.4
QUANTIZER–AC CHARACTERISTICS
Upper –3 dB Bandwidth
Small Signal Gain
Differential
S11 @ 2.5 GHz
www.DataShIenept4uUt .Rcoemsistance
Differential
Input Capacitance
Pulsewidth Distortion2
QUANTIZER SLICE ADJUSTMENT
Gain
SliceP–SliceN = ؎0.5 V
Control Voltage Range
SliceP–SliceN
Control Voltage Range
@ SliceP or SliceN
Slice Threshold Offset
0.115
–0.8
1.3
LEVEL SIGNAL DETECT (SDOUT)
Level Detect Range (See Figure 2) RTHRESH = 2 k
RTHRESH = 20 k
RTHRESH = 90 k
Response TimeDC-Coupled
Hysteresis (Electrical), PRBS 223 RTHRESH = 2 k
RTHRESH = 20 k
RTHRESH = 90 k
LOSS OF LOCK DETECT (LOL)
LOL Response Time
From fVCO error > 1000 ppm
POWER SUPPLY VOLTAGE
9.4
2.5
0.7
0.1
5.6
3.9
3.2
3.0
POWER SUPPLY CURRENT
150
PHASE-LOCKED LOOP
CHARACTERISTICS
Jitter Transfer BW
Jitter Peaking
Jitter Generation
PIN–NIN = 10 mV p-p
OC-48
OC-48
OC-48, 12 kHz–20 MHz
Jitter Tolerance
OC-48 (See Figure 9)
600 Hz
6 kHz
100 kHz
1 MHz
923
203
5.5
1.03
Typ
4
2
500
244
1.9
54
–15
100
0.65
10
0.200
± 1.0
13.3
5.3
3.0
0.3
6.6
6.1
6.7
60
3.3
164
590
0.025
0.05
Max Unit
1.2 V
2.4 V
V
10 mV p-p
5 mV p-p
µV
µV rms
GHz
dB
dB
pF
ps
0.300
+0.8
VCC
V/V
V
V
mV
18.0 mV
7.6 mV
5.2 mV
5 µs
7.8 dB
8.5 dB
9.9 dB
µs
3.6 V
215 mA
880
0.0033
0.09
kHz
dB
UI rms
UI p-p
UI p-p
UI p-p
UI p-p
UI p-p
–2– REV. A


Features a OC-48/OC-48 FEC Clock and Data Recove ry IC with Integrated Limiting Amp ADN2 811 PRODUCT DESCRIPTION FEATURES Meets SONET Requirements for Jitter Transfer / Generation/Tolerance Quantizer Sensit ivity: 4 mV Typ Adjustable Slice Level: ؎ 100 mV 1.9 GHz Minimum Bandwidth Pa tented Clock Recovery Architecture Loss of Signal Detect Range: 3 mV to 15 mV www.DataSheet4U.com Single Reference Cl ock Frequency for Both Native SONET and 15/14 (7%) Wrapper Rate Choice of 19.4 4 MHz, 38.88 MHz, 77.76 MHz, or 155.52 MHz REFCLK LVPECL/LVDS/LVCMOS/LVTTL Com patible Inputs (LVPECL/LVDS Only at 155 .52 MHz) 19.44 MHz Oscillator On-Chip t o Be Used with External Crystal Loss of Lock Indicator Loopback Mode for High Speed Test Data Output Squelch and Bypa ss Features Single-Supply Operation: 3. 3 V Low Power: 540 mW Typical 7 mm ؋ 7 mm 48-Lead LFCSP APPLICATIONS SONET OC -48, SDH STM-16, and 15/14 FEC WDM Tran sponders Regenerators/Repeaters Test Eq uipment Backplane Applications The ADN2811 provides the receiver.
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