Document
BB506C
Built in Biasing Circuit MOS FET IC UHF RF Amplifier
REJ03G1246-0100 Rev.1.00 Jun. 27, 2005
Features
• Built in Biasing Circuit; To reduce using parts cost & PC board space. • High gain www.DataSheet4U.com PG = 24 dB typ. (f = 900 MHz) • Low noise NF = 1.4 dB typ. (f = 900 MHz) • Low output capacitance Coss = 1.1 pF typ. (f = 1 MHz) • Provide mini mold packages: CMPAK-4 (SOT-343mod)
Outline
RENESAS Package code: PTSP0004ZA-A (Package name: CMPAK-4)
2 3 1 4
1. Source 2. Gate1 3. Gate2 4. Drain
Notes:
1. Marking is “FS-“. 2. BB506C is individual type number of RENESAS BBFET.
Absolute Maximum Ratings
(Ta = 25°C)
Item Drain to source voltage Gate1 to source voltage Gate2 to source voltage Symbol VDS VG1S VG2S Ratings 6 +6 –0 +6 –0 30 250 150 –55 to +150 Unit V V V mA mW °C °C
Drain current ID Channel power dissipation PchNote3 Channel temperature Tch Storage temperature Tstg Notes: 3. Value on the glass epoxy board (50 mm × 40 mm × 1 mm).
Rev.1.00
Jun. 27, 2005,
page 1 of 8
BB506C
Electrical Characteristics
(Ta = 25°C)
Item Drain to source breakdown voltage Gate1 to source breakdown voltage Gate2 to source breakdown voltage Gate1 to source cutoff current Gate2 to source cutoff current www.DataSheet4U.com Gate1 to source cutoff voltage Gate2 to source cutoff voltage Drain current Forward transfer admittance Input capacitance Output capacitance Power gain Noise figure Symbol V(BR)DSS V(BR)G1SS V(BR)G2SS IG1SS IG2SS VG1S(off) VG2S(off) ID(op) |yfs| Ciss Coss PG NF Min 6 +6 +6 — — 0.5 0.4 12 27 1.2 0.7 19 — Typ — — — — — 0.8 0.7 16 32 1.6 1.1 24 1.4 Max — — — +100 +100 1.1 1.0 20 38 2.0 1.5 29 2.1 Unit V V V nA nA V V mA mS pF pF dB dB Test Conditions ID = 200 µA, VG1S = VG2S = 0 IG1 = +10 µA, VG2S = VDS = 0 IG2 = +10 µA, VG1S = VDS = 0 VG1S = +5 V, VG2S = VDS = 0 VG2S = +5 V, VG1S = VDS = 0 VDS = 5 V, VG2S = 4 V, ID = 100 µA VDS = 5 V, VG1S = 5 V, ID = 100 µA VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 kΩ VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 kΩ, f = 1 kHz VDS = 5 V, VG1 = 5 V, VG2S = 4 V RG = 100 kΩ, f = 1 MHz VDS = 5 V, VG1 = 5V, VG2S = 4 V RG = 100 kΩ, f = 900 MHz
Bias Circuit for Operating Items (ID(op), |yfs|, Ciss, Coss, NF, PG)
VG2 Gate 2 Gate 1 RG VG1
Drain A ID
Source
Rev.1.00
Jun. 27, 2005,
page 2 of 8
BB506C
900 MHz Power Gain, Noise Figure Test Circuit
VG1 VG2 C4 C5 VD C6
R1
R2 C3 G2
R3 D L3
RFC Output (50 Ω) L4
Input (50 Ω)
G1 S L1 L2
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C1
C2
C1, C2 C3 C4 to C6 R1 R2 R3
: : : : : :
Variable Capacitor (10 pF MAX) Disk Capacitor (1000 pF) Air Capacitor (1000 pF) 100 kΩ 47 kΩ 4.7 kΩ
L1: 10
L2:
10
26
(φ1 mm Copper wire) Unit : mm
8
21 L4: 29
3
L3:
18
10
7
7
RFC : f1 mm Copper wire with enamel 4 turns inside dia 6 mm
Rev.1.00
Jun. 27, 2005,
page 3 of 8
10
3
BB506C
Main Characteristics
Maximum Channel Power Dissipation Curve
Channel Power Dissipation Pch* (mW)
400 25
Typical Output Characteristics
VG2S = 4 V VDS = VG1 20
82 kΩ
68 kΩ
300
ID (mA)
15
100 kΩ
120 kΩ
200
Drain Current
10
kΩ
150 kΩ
100
5
RG
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0 50 100 150 200 0 0
=1
80
1
2
3
4
5
Ambient Temperature Ta (°C)
* Value on the glass epoxy board (50 mm × 40 mm × 1 mm)
Drain to Source Voltage VDS (V) Forward Transfer Admittance vs. Gate1 Voltage
|yfs| (mS)
50 VDS = 5 V VG2S =4 V RG = 100 kΩ f = 1 kHz
Drain Current vs. Gate1 Voltage
25 VDS = 5 V VG2S = 4 V RG = 100 kΩ
ID (mA)
20
40
Forward Transfer Admittance
4V
15
4V 3V
3V 2V
30 20
Drain Current
10 5
VG2S = 1 V
0 0 1 2 3 4 5
10 V G2S = 0
2V 1V
0
0
1
2
3
4
5
Gate1 Voltage VG1 (V)
Gate1 Voltage VG1 (V)
Drain Current vs. Gate Resistance
25
5
Input Capacitance vs. Gate2 to Source Voltage
VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 1 MHz
Input Capacitance Ciss (pF)
100 1000
Drain Current ID (mA)
20
4
15
3
10 5 VDS = VG1 = 5 V VG2S = 4 V 0 10
2
1
0 0 1 2 3 4
Gate Resistance RG (kΩ)
Gate2 to Source Voltage VG2S (V)
Rev.1.00
Jun. 27, 2005,
page 4 of 8
BB506C
Power Gain vs. Gate Resistance
50
VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz
Noise Figure vs. Gate Resistance
5
VDS = 5 V VG1 = 5 V VG2S = 4 V f = 900 MHz
Power Gain PG (dB)
NF (dB) Noise Figure
40
4
30
3
20
2
10
1
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0 10
0 100 1000 10 100 1000
Gate Resistance RG (kΩ) Power Gain vs. Gate2 to Source Voltage
25
5
Gate Resistance RG (kΩ)
Noise Figure vs. Gate2 to Source Voltage
VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 900 MHz
NF (dB) Noise Figure
4 VDS = 5 V VG1 =5 V RG = 100 kΩ f = 900 MHz 1 2 3
Power Gain PG (dB)
20
4
15
3 2
10
5
1
0
0 1 2 3 4
Gate2 to Source Voltage VG2S (V) Gain Reduction vs. Gate2 to Source Voltage
40 VDS = 5 V VG1 = 5 V RG = 100 kΩ f = 900 MHz
Gate2 to Source Voltage
VG2S (V)
Gain Reduction GR (dB)
35 30 25 20 15 10 5 0 0 1 2
3
4
Gate2 to Source Voltage VG2S (V)
Rev.1.00
Jun. 27, 2005,
page 5 of 8
BB506C
S11 Parameter vs. Frequency
.8 .6 .4 3 .2 4 5 10 0 .2 .4 .6 .8 1 1.5 2 3 45 –10 –.2 –5 –4 –3 –.4 –2 –.6 –.8 –1 –1.5 –120° –90° –60° 18.