74AHCT2G00 device Datasheet

74AHCT2G00 Datasheet PDF, Equivalent


Part Number

74AHCT2G00

Description

high-speed Si-gate CMOS device

Manufacture

NXP Semiconductors

Total Page 17 Pages
PDF Download
Download 74AHCT2G00 Datasheet PDF


74AHCT2G00
INTEGRATED CIRCUITS
DATA SHEET
www.DataSheet4U.com
74AHC2G00; 74AHCT2G00
2-input NAND gate
Product specification
2004 Jan 21

74AHCT2G00
Philips Semiconductors
2-input NAND gate
Product specification
74AHC2G00; 74AHCT2G00
FEATURES
Symmetrical output impedance
High noise immunity
ESD protection:
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
www.DataSheet4U.cCoDmM EIA/JESD22-C101 exceeds 500 V.
Low power dissipation
Balanced propagation delays
SOT505-2 and SOT765-1 package
Specified from 40 to +85 °C and 40 to +125 °C.
DESCRIPTION
The 74AHC2G/AHCT2G00 is a high-speed Si-gate CMOS
device.
The 74AHC2G/AHCT2G00 provides the 2-input NAND
gate function.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
CI
CPD
propagation delay nA and nB to nY
input capacitance
power dissipation capacitance per
gate
CL = 15 pF; VCC = 5 V
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi × N + Σ(CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts;
N = total load switching outputs;
Σ(CL × VCC2 × fo) = sum of the outputs.
2. The condition is VI = GND to VCC.
TYPICAL
AHC2G
3.5
1.5
17
AHCT2G
3.6
1.5
18
UNIT
ns
pF
pF
2004 Jan 21
2


Features INTEGRATED CIRCUITS DATA SHEET www.Data Sheet4U.com 74AHC2G00; 74AHCT2G00 2-in put NAND gate Product specification 20 04 Jan 21 Philips Semiconductors Prod uct specification 2-input NAND gate F EATURES • Symmetrical output impedanc e • High noise immunity • ESD prote ction: – HBM EIA/JESD22-A114-A exceed s 2000 V – MM EIA/JESD22-A115-A excee ds 200 V www.DataSheet4U.com 74AHC2G00 ; 74AHCT2G00 DESCRIPTION The 74AHC2G/AH CT2G00 is a high-speed Si-gate CMOS dev ice. The 74AHC2G/AHCT2G00 provides the 2-input NAND gate function. – CDM EI A/JESD22-C101 exceeds 500 V. • Low p ower dissipation • Balanced propagati on delays • SOT505-2 and SOT765-1 pac kage • Specified from −40 to +85 ° C and −40 to +125 °C. QUICK REFERENC E DATA GND = 0 V; Tamb = 25 °C; tr = t f ≤ 3.0 ns. TYPICAL SYMBOL tPHL/tPLH CI CPD Notes 1. CPD is used to determin e the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi × N + Σ( CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load ca.
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