74AHCT2G241 driver Datasheet

74AHCT2G241 Datasheet PDF, Equivalent


Part Number

74AHCT2G241

Description

Dual buffer/line driver

Manufacture

NXP Semiconductors

Total Page 17 Pages
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Download 74AHCT2G241 Datasheet PDF


74AHCT2G241
74AHC2G241; 74AHCT2G241
Dual buffer/line driver; 3-state
Rev. 3 — 13 May 2013
Product data sheet
1. General description
The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device.
The 74AHC2G241; 74AHCT2G241 is a dual non-inverting buffer/line driver with 3-state
outputs. The 3-state outputs are controlled by the output enable inputs 1OE and 2OE. A
HIGH level at pin 1OE causes output 1Y to assume a high-impedance OFF-state. A LOW
level at pin 2OE causes output 2Y to assume a high-impedance OFF-state.
Schmitt-trigger action at all inputs makes the circuit highly tolerant for slower input rise
and fall times.
2. Features and benefits
Symmetrical output impedance
High noise immunity
ESD protection:
HBM JESD22-A114E: exceeds 2000 V
MM JESD22-A115-A: exceeds 200 V
CDM JESD22-C101C: exceeds 1000 V
Low power dissipation
Balanced propagation delays
Multiple package options
Specified from 40 C to +85 C and from 40 C to +125 C
3. Ordering information
Table 1. Ordering information
Type number
Package
Temperature range Name
74AHC2G241DP 40 C to +125 C TSSOP8
74AHCT2G241DP
74AHC2G241DC 40 C to +125 C VSSOP8
74AHCT2G241DC
74AHC2G241GD 40 C to +125 C XSON8
74AHCT2G241GD
Description
plastic thin shrink small outline package; 8 leads;
body width 3 mm; lead length 0.5 mm
Version
SOT505-2
plastic very thin shrink small outline package; 8 leads; SOT765-1
body width 2.3 mm
plastic extremely thin small outline package; no leads; SOT996-2
8 terminals; body 3 2 0.5 mm

74AHCT2G241
NXP Semiconductors
74AHC2G241; 74AHCT2G241
Dual buffer/line driver; 3-state
4. Marking
Table 2. Marking
Type number
74AHC2G241DP
74AHCT2G241DP
74AHC2G241DC
74AHCT2G241DC
74AHC2G241GD
74AHCT2G241GD
Marking code[1]
A241
C241
A41
C41
A41
C41
[1] The pin 1 indicator is located on the lower left corner of the device, below the marking code.
5. Functional diagram
1 1OE
2 1A
7 2OE
5 2A
1Y 6
2Y 3
Fig 1. Logic symbol
001aaa409
6. Pinning information
6.1 Pinning
74AHC2G241
74AHCT2G241
1OE 1
1A 2
2Y 3
GND 4
8 VCC
7 2OE
6 1Y
5 2A
001aaj391
Fig 3. Pin configuration SOT505-2 (TSSOP8) and
SOT765-1 (VSSOP8)
2
1
1
EN1
6
5
7
2
EN2
3
001aaa408
Fig 2. IEC logic symbol
74AHC2G241
74AHCT2G241
1OE 1
1A 2
8 VCC
7 2OE
2Y 3
6 1Y
GND 4
5 2A
001aaj392
Transparent top view
Fig 4. Pin configuration SOT996-2 (XSON8)
74AHC_AHCT2G241
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 13 May 2013
© NXP B.V. 2013. All rights reserved.
2 of 17


Features 74AHC2G241; 74AHCT2G241 Dual buffer/lin e driver; 3-state Rev. 3 — 13 May 201 3 Product data sheet 1. General descr iption The 74AHC2G241; 74AHCT2G241 is a high-speed Si-gate CMOS device. The 7 4AHC2G241; 74AHCT2G241 is a dual non-in verting buffer/line driver with 3-state outputs. The 3-state outputs are contr olled by the output enable inputs 1OE a nd 2OE. A HIGH level at pin 1OE causes output 1Y to assume a high-impedance OF F-state. A LOW level at pin 2OE causes output 2Y to assume a high-impedance OF F-state. Schmitt-trigger action at all inputs makes the circuit highly toleran t for slower input rise and fall times. 2. Features and benefits  Symmetri cal output impedance  High noise imm unity  ESD protection:  HBM JESD2 2-A114E: exceeds 2000 V  MM JESD22-A 115-A: exceeds 200 V  CDM JESD22-C10 1C: exceeds 1000 V  Low power dissip ation  Balanced propagation delays Multiple package options  Specifi ed from 40 C to +85 C and from 40 C to +125 C.
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