Bus Driver. PI74ALVC162334 Datasheet

PI74ALVC162334 Driver. Datasheet pdf. Equivalent


Part PI74ALVC162334
Description 16-Bit Universal Bus Driver
Feature 1234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234.
Manufacture Pericom Semiconductor Corporation
Datasheet
Download PI74ALVC162334 Datasheet


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PI74ALVC162334
PI74ALVC162334
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16-Bit Universal Bus Driver
with 3-State Outputs
Product Features
• PI74ALVC162334 is designed for low voltage operation,
VCC = 2.3V to 3.6V
• Outputs have equivalent 26 ohm series resistors
• Supports PC100 Registered DIMM
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• Typical VOLP (Output Ground Bounce) < 0.8V
at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) < 2.0V
at VCC = 3.3V, TA = 25°C
• Industrial operation at –40°C to +85°C
• Packages available:
– 48-pin 240 mil wide plastic TSSOP (A48)
– 48-pin 173 mil wide plastic TVSOP (K48)
– 48-pin 300 mil wide plastic SSOP (V48)
Logic Block Diagram
Product Description
Pericom Semiconductor’s PI74ALVC series of logic circuits
are produced in the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The 16-bit PI74ALVC162334 universal bus driver is designed
for 2.3V to 3.6V Vcc operation.
Data flow from A to Y is controlled by Output Enable (OE).
The device operates in the transparent mode when LE is LOW.
When LE is HIGH, the A data is latched if CLK is held at a high
or low logic level. If LE is HIGH, the A-data is stored in the
latch/flip-flop on the low-to-high transition of CLK. When OE is
HIGH, the outputs are in the high-impedance state.
The outputs have equivalent 26 ohm series resistors to reduce
overshoot and undershoot.
To ensure the high-impedance state during power up or power
down, OE should be tied to Vcc through a pullup resistor; the
minimum value of the resistor is determined by the current-
sinking capability of the driver.
1
PS8313
08/04/98



PI74ALVC162334
PI74ALVC162334
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Product Pin Description
Pin Name Description
OE Output Enable Input (Active LOW)
LE Latch Enable (Active LOW)
CLK Clock Input
A Data Input
Y Data Output
GND
Ground
VCC Power
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Product Pin Configuration
OE
Y1
Y2
GND
Y3
Y4
VCC
Y5
Y6
GND
Y7
Y8
Y9
Y10
GND
Y11
Y12
VCC
Y13
Y14
GND
Y15
Y16
NC
48-PIN
A-48
K-48
V-48
CLK
A1
A2
GND
A3
A4
VCC
A5
A6
GND
A7
A8
A9
A10
GND
A11
A12
VCC
A13
A14
GND
A15
A16
LE
Truth Table(1)
Inputs
Outputs
OE LE CLK A
Y
HXXXZ
LLXLL
L LXHH
LHLL
L H HH
L
H L or H X
Yo(2)
Note:
1 H = High Signal Level
L = Low Signal Level
Z = High Impedance
= Transition LOW-to-HIGH
X = Irrelevant
2. Output level before the indicated steady-state input
conditions were established.
2
PS8313
08/04/98







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