PI74ALVC162834FD Driver Datasheet

PI74ALVC162834FD Datasheet PDF, Equivalent


Part Number

PI74ALVC162834FD

Description

16-Bit Universal Bus Driver

Manufacture

Pericom Semiconductor Corporation

Total Page 5 Pages
Datasheet
Download PI74ALVC162834FD Datasheet


PI74ALVC162834FD
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18-Bit Universal Bus Driver
with 3-State Outputs
Product Features
• PI74ALVC162834F is designed for low voltage operation,
VCC = 2.3V to 3.6V
• Data inputs have clamp diodes to VCC
www.DataS•heOeut4tUpu.ctosmhave equivalent 26series resistors
• Supports PC133 Registered DIMM
• Typical VOLP (Output Ground Bounce)
< 0.8V at VCC = 3.3V, TA = 25°C
• Typical VOHV (Output Voh Undershoot)
< 2.0V at VCC = 3.3V, TA= 25°C
• Industrial operation at –40°C to +85°C
• Packages available:
– 56-pin 240 mil wide plastic TSSOP (A)
– 56-pin 173 mil wide plastic TVSOP (K)
– 56-pin 300 mil wide plastic SSOP (V)
Product Description
Pericom Semiconductor’s PI74ALVC series of logic circuits
are produced using the Company’s advanced 0.5 micron CMOS
technology, achieving industry leading speed.
The 18-bit PI74ALVC162834FD universal bus driver is designed
for 2.3V to 3.6V VCC operation.
Data flow from A to Y is controlled by Output Enable (OE).
The device operates in the transparent mode when LE is LOW. The
A data is latched if CLK is held at a high or low logic level. If LE
is HIGH, the A-bus is stored in the latch/flip-flop on the low-to-high
transition of CLK. When OE is HIGH, the outputs are in the high-
impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to VCC through a pullup resistor; the
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Logic Block Diagram
27
OE
30
CLK
28
LE
54
A1
1D
C1
CLK
3 Y1
TO 17 OTHER CHANNELS
1 PS8475 04/25/00

PI74ALVC162834FD
PI74ALVC162834FD
18-Bit Universal Bus Driver with 3-State Outputs
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Product Pin Description
Pin Name
OE
LE
CLK
A
Y
GND
VCC
www.DataSheet4U.com
Description
Output Enable Input (Active LOW)
Latch Enable (Active LOW)
Clock Input
Data Input
Data Output
Ground
Power
Product Pin Configuration
NC
NC
Y1
GND
Y2
Y3
VCC
Y4
Y5
Y6
GND
Y7
Y8
Y9
Y10
Y11
Y12
GND
Y13
Y14
Y15
VCC
Y16
Y17
GND
Y18
OE
LE
1 56
2 55
3 54
4 53
5 52
6 51
7 50
8 49
9 48
10 47
11 46
12 45
13 44
14 56-Pin 43
15 A,K,V 42
16 41
17 40
18 39
19 38
20 37
21 36
22 35
23 34
24 33
25 32
26 31
27 30
28 29
GND
NC
A1
GND
A2
A3
VCC
A4
A5
A6
GND
A7
A8
A9
A10
A11
A12
GND
A13
A14
A15
VCC
A16
A17
GND
A18
CLK
GND
Truth Table(1)
Inputs
Outputs
OE LE CLK A
Y
HXXXZ
L LXL L
L LXHH
LHLL
L H HH
L H H X Yo(2)
L H L X Yo(3)
Notes:
1 H = High Signal Level
L = Low Signal Level
Z = High Impedance
= Transition LOW-to-HIGH
X = Irrelevant
2. Output level before the indicated steady-state input
conditions were established, provided that CLK is
HIGH before LE goes HIGH.
3. Output level before the indicated steady-state input
conditions were established.
2 PS8475 04/25/00


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