Explanation of Serial Data of CDS Part
Serial data of CDS part has the following functions.
• PGA gain (D5 to D12 of register 0)
Details are referred to page 5 block diagram.
At CDS_in mode: –2.36 dB + 0.132 dB × N (Log linear)
At ADC_in mode: 0.57 times + 0.01784 times × N (Times linear)
∗: Full-scale digital output is defined as 0 dB when 1 V is input.
Above PGA gain definition means input signal 1 Vp-p to CDS_in, and set N = 18 (correspond 2.36 dB), and then
PGA outputs the 2 V full-range, and also ADC out puts the full code (1023).
This mean offset gain of PGA has 6 dB – 2.36 dB = 3.64 dB, therefore it should be decided that how much dB add
0 dB when set N = 18 which correspond to 2.36 dB
(1) Level dia explain
2 V 1023
(CDS = 0 dB)
3.64 dB + 0.132 dB × N
(2) Level dia on the circuit
• CSEL (D15 of register 0)
Data = 0: Select CDSIN
Data = 1: Select ADCIN
Figure 8 Level Dia of PGA
D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8
• SLP and STBY (D3, D4 of register 1)
SLP: Stop the all circuit. Consumption current of CDS part is less than 10 µA.
Start up from offset calibration when recover is needed.
STBY: Only the standard voltage generating circuit is operated. Consumption current of CDS part is about 3 mA.
Allow 50 H time for feedback clamp is stabilized until recover.
• Output mode (D5 to D7 of register 1 and D4 of register 3)
It is a test mode. Combination details are table 3 to 5. Normally set to all 0.
• SHA-fsel (D8 to D9 of register 1)
It is a LPF switching of SH amplifier. Frequency characteristics are referred to page 8. To get rough idea, set the
double cut off frequency point with using.
• SHSW-fsel (D10 to D13 of register 1)
It is a time constant which sampling the black level of SH amplifier. Frequency characteristics are referred to page
8. To get rough idea, set the double cut off frequency point with using. S/N changes by this data, so find the
appropriate point with set data to up/down.
Rev.1.0 Apr 20, 2004 page 13 of 21