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HD49340NP/HNP
CDS/PGA & 10-bit A/D Converter
REJ03F0109-0100Z Rev.1.0 Apr 20, 2004
Description
The HD49340NP/HNP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter in a single chip.
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Functions
• • • • • • • Correlated double sampling PGA Offset compensation Serial interface control 10-bit ADC Operates using only the 3 V voltage Corresponds to switching mode of power dissipation and operating frequency Power dissipation: 120 mW (Typ), maximum frequency: 36 MHz (HD49340HNP) Power dissipation: 60 mW (Typ), maximum frequency: 25 MHz (HD49340NP) • ADC direct input mode • QFN 36-pin package
Features
• Suppresses low-frequency noise output from CCD by the S/H type correlated double sampling. • The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. • High sensitivity is achieved due to the high S/N ratio and a wide coverage provided by a PG amplifier. • Feedback is used to compensate and reduce the DC offsets including the output DC offset due to PGA gain change and the CCD offset in the CDS (correlated double sampling) amplifier input. • PGA, standby mode, etc., is achieved via a serial interface. • High precision is provided by a 10-bit-resolution A/D converter.
Rev.1.0 Apr 20, 2004 page 1 of 21
HD49340NP/HNP
Pin Arrangement
ADCIN AVSS AVDD BIAS BLKC CDSIN BLKFB BLKSH AVDD
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VRM VRT VRB DVDD DVSS CS SDATA SCK D0
27 26 25 24 23 22 21 20 19 28 18 29 17 30 16 31 15 32 14 33 13 34 12 35 11 36 10 1 2 3 4 5 6 7 8 9 D1 D2 D3 D4 D5 D6 D7 D8 D9 (Top view)
AVSS SPSIG SPBLK OBP PBLK DVDD ADCLK DVSS DRDVDD
Pin Description
Pin No. 1 to 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Symbol D0 to D9 DRDVDD DVSS ADCLK DVDD PBLK OBP SPBLK SPSIG AVSS AVDD BLKSH BLKFB CDSIN BLKC BIAS AVDD AVSS ADCIN VRM VRT VRB Description Digital output Output buffer power supply (3 V) Digital ground (0 V) ADC conversion clock input pin Digital power supply (3 V) Preblanking input pin Optical black pulse input pin Black level sampling clock input pin Signal level sampling clock input pin Analog ground (0 V) Analog power supply (3 V) Black level S/H pin Black level FB pin CDS input pin Black level C pin Internal bias pin Connect a 33 kΩ resistor between BIAS and AVSS. Analog power supply (3 V) Analog ground (0 V) ADC input pin Reference voltage pin 1 Connect a 0.1 µF ceramic capacitor between VRM and AVSS. Reference voltage pin 3 Connect a 0.1 µF ceramic capacitor between VRT and AVSS. Reference voltage pin 2 Connect a 0.1 µF ceramic capacitor between VRB and AVSS. I/O O — — I — I I I I — — — — I — — — — — — — — Analog(A) or Digital(D) D D D D D D D D D A A A A A A A A A A A A A
Rev.1.0 Apr 20, 2004 page 2 of 21
HD49340NP/HNP
Pin Description (cont.)
Pin No. 31 32 33 34 35 36 Note: Symbol DVDD DVSS CS SDATA SCK D0 Description Digital power supply (3 V) Digital ground (0 V) Serial interface control input pin Serial data input pin Serial clock input pin Digital output I/O — — I I I O Analog(A) or Digital(D) D D D D D D
1. With pull-down resistor.
Input/Output Equivalent Circuit
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Pin Name Digital output D0 to D9
Equivalent Circuit
DIN STBY DVDD Digital output
Digital input
ADCLK, OBP, SPBLK, SPSIG, CS, SCK, SDATA, PBLK CDSIN
DVDD Digital input
Analog
AVDD CDSIN
Internally connected to VRT
ADCIN
ADCIN
AVDD
Internally connected to VRM
BLKSH, BLKFB, BLKC
BLKFB
AVDD
+ −
BLKSH BLKC
VRT, VRM, VRB
VRT
+ −
+ −
VRM VRB AVDD
+ −
BIAS
BIAS
AVDD
Rev.1.0 Apr 20, 2004 page 3 of 21
HD49340NP/HNP
Block Diagram
DRDVDD ADCLK SPBLK SPSIG DVDD AVDD DVSS AVSS
16 18 19 Timing generator
31 16 18 19 19 42 OEB
ADCIN 27 PBLK 26 CDSIN 26 BLKSH 28
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9 D9 CDS PGA 10bit ADC 8 D8 7 D7 6 D6 5 D5 4 D4 3 D3 2 D2 D1 D0
BLKC 28
BLKFB 29
DC offset compensation circuit
Serial interface
Bias generator
17
44 45 43
35
32 34 33
VRT
VRM
SDATA
Rev.1.0 Apr 20, 2004 page 4 of 21
BIAS
OBP
VRB
SCK
CS
Output latch circuit
HD49340NP/HNP
Internal Functions
Functional Description • CDS input CCD low-frequency noise is suppressed by CDS (correlated double sampling). The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1 Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *2 • ADC input The center level of the input signal is clamped at 512 LSB (Typ). Gain can be adjusted using 8 bits of register (0.01784 times steps) within the range from 0.57 times (–4.86 dB) to 5.14 times (14.22 dB). *1 • Automatic offset calibration of PGA and ADC • DC offset compensation feedback for CCD and CDS www.DataSheet4U.com • Pre-blanking CDS input operation is protected by separating it from the large input signal. Digital output is set at clamp level by resister. • Digital output enable function No.