• CDS input
CCD low-frequency noise is suppressed by CDS (correlated double sampling).
The signal level is clamped at 14 LSB to 76 LSB by resister during the OB period. *1
Gain can be adjusted using 8 bits of register (0.132 dB steps) within the range from –2.36 dB to 31.40 dB. *2
• ADC input
The center level of the input signal is clamped at 512 LSB (Typ).
Gain can be adjusted using 8 bits of register (0.01784 times steps) within the range from 0.57 times (–4.86 dB)
to 5.14 times (14.22 dB). *1
• Automatic offset calibration of PGA and ADC
• DC offset compensation feedback for CCD and CDS
CDS input operation is protected by separating it from the large input signal.
Digital output is set at clamp level by resister.
• Digital output enable function
Notes: 1. It is not covered by warranty when 14LSB settings
2. Full-scale digital output is defined as 0 dB (one time) when 1 V is input.
Figure 1 shows CDS/PGA + ADC function block.
D0 to D9
Figure 1 HD49340NP/HNP Functional Block Diagram
1. CDS (Correlated Double Sampling) Circuit
The CDS circuit extracts the voltage differential between the black level and a signal including the black level. The
black level is directly sampled at C1 by using the SPBLK pulse, buffered by the SHAMP, then provided to the
The signal level is directly sampled at C2 by using the SPSIG pulse, and provided to CDSAMP (see figure 1). The
difference between these two signal levels is extracted by the CDSAMP, which also operates as a programmable
gain amplifier at the previous stage. The CDS input is biased with VRT (2 V) during the SPBLK pulse validation
period. During the PBLK period, the above sampling and bias operation are paused.
Rev.1.0 Apr 20, 2004 page 5 of 21