LH531000B

LH531000B FEATURES 131,072 words × 8 bit organization Access time: 150 ns (MAX.) Low power consumption: Operating: 192.5 mW (MAX.) Standby: 550 µW (MAX.) Programmable CE/OE/OE Static operation TTL compatible I/O Three-state outputs Single +5 V power supply Packages: 28-pin, 600-mil DIP 28-pin, 450-mil SOP Mask ROM specific pinout CMOS 1M (128K × 8) MROM DESCRIPTION The LH531000B is a mask-programmable ROM organized as 131,072 × 8 bits. It is fabricated using silicon-gate CMOS process technology. PIN CONNECTIONS 28-PIN DIP 28-PIN SOP TOP VIEW A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC A14 A13 A8 A9 A11 A16 A10 CE /OE/OE D7 D6 D5 D4 D3 531000B-1 Figure 1. Pin Connections for DIP and SOP Packages 1 LH531000B CMOS 1M MROM A16 22 A15 1 A14 27 A13 26 A10 21 A9 24 A8 25 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 ADDRESS DECODER ADDRESS BUFFER A12 2 A11 23 MEMORY MATRIX (131,072 x 8) COLUMN SELECTOR SENSE AMPLIFIER CE/OE/OE 20 CE/OE BUFFER TIMING GENERATOR OUTPUT BUFFER 28 14 VCC GND 11 D0 12 D1 13 D2 15 D3 16 D4 17 D5 18 D6 19 D7 531000B-2 Figure 2. LH531000B Block Diagram PIN DESCRIPTION SIGNAL PIN NAME NOTE SIGNAL PIN NAME NOTE A0 - A16 D0 - D7 CE/OE/OE Address input Data output Chip Enable input or Output Enable input 1 VCC GND Power supply (+5 V) Ground NOTE: 1. Active level of CE/OE/OE is mask-programmable. TRUTH TABLE PIN 20 CE OE/OE MODE D0...