LH532000B

LH532000B FEATURES 262,144 words × 8 bit organization (Byte mode) 131,072 words × 16 bit organization (Word mode) BYTE input pin selects bit configuration Access times: 120/150 ns (MAX.) Low-power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.) Programmable OE/OE and OE1/OE1/DC Static operation TTL compatible I/O Three-state outputs Single +5 V power supply Packages: 40-pin, 600-mil DIP 40-pin, 525-mil SOP 48-pin, 12 × 18 mm2 TSOP (Type I) ×16 word-wide pinout DESCRIPTION The LH532000B is a 2M-bit mask-programmable ROM with two programmable memory organizations, byte and word modes. It is fabricated using silicon-gate CMOS process technology. CMOS 2M (256K × 8/128K × 16) MROM PIN CONNECTIONS 40-PIN DIP 40-PIN SOP TOP VIEW OE1/OE1/DC A7 A6 A5 A4 A3 A2 A1 A0 CE GND OE/OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 48 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE GND D15/A-1 (LSB) D7 D14 D6 D13 D5 D12 D4 VCC 532000B-1 Figure 1. Pin Connections for DIP and SOP Packages 1 LH532000B CMOS 2M MROM 48-PIN TSOP (Type I) BYTE A16 A15 A14 A13 A12 A11 A10 A9 A8 NC GND NC NC OE1/OE1/DC A7 A6 A5 A4 A3 A2 A1 A0 CE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND GND D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC VCC GND D11 D3 D10 D2 D9 D1 D8 D0 OE/OE GND GND NOTE: Reverse ben...