CMOS 2M (256K x 8) MROM
LH532100B-1
FEATURES • 262,144 words × 8 bit organization • Access time: 120 ns (MAX.) • Static operation • TTL compatib...
Description
LH532100B-1
FEATURES 262,144 words × 8 bit organization Access time: 120 ns (MAX.) Static operation TTL compatible I/O Three-state outputs Single +5 V power supply Power consumption: Operating: 275 mW (MAX.) Standby: 550 µW (MAX.) Mask-programmable control pin: Pin 1 = OE1/OE1/DC Pin 24 = OE/OE Packages: 32-pin, 600-mil DIP 32-pin, 525-mil SOP 32-pin, 450-mil QFJ (PLCC) 32-pin, 8 × 20 mm2 TSOP (Type I) 32-pin, 400-mil TSOP (Type II) DESCRIPTION
The LH532100B-1 is a CMOS 2M-bit mask-programmable ROM organized as 262,144 × 8 bits. It is fabricated using silicon-gate process technology.
D7 CE A10 OE/OE A11 A9 A8 A13 A14 21 22 23 24 25 26 27 28 29
32-PIN DIP 32-PIN SOP OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND
CMOS 2M (256K × 8) MROM
PIN CONNECTIONS
TOP VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
VCC DC A17 A14 A13 A8 A9 A11 OE/OE A10 CE D7 D6 D5 D4 D3
532100B1-1
Figure 1. Pin Connections for DIP and SOP Packages
GND
32-PIN QFJ
TOP VIEW
D6
D5
D4
D3
D2
20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 30 31 32 1 2 3 4 D0 A0 A1 A2 A3 A4 A5 A6 A7
VCC
DC
A16
A15
OE1/OE1/DC
A17
A12
D1
532100B1-7
Figure 2. Pin Connections for QFJ (PLCC) Package
1
LH532100B-1
CMOS 2M MROM
32-PIN TSOP (Type I)
TOP VIEW
32-PIN TSOP (Type II)
TOP VIEW
A11 A9 A8 A13 A14 A17 DC VCC OE1/OE1/DC A16 A15 A12 A7 A6 A5 A4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18...
Similar Datasheet