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LH53B16R00 Dataheets PDF



Part Number LH53B16R00
Manufacturers Sharp Electrionic Components
Logo Sharp Electrionic Components
Description CMOS 16M (1M x 16/512K x 32) MROM
Datasheet LH53B16R00 DatasheetLH53B16R00 Datasheet (PDF)

LH53B16R00 FEATURES • 1,048,576 × 16 bit organization (Word mode: W = VIL) 524,288 × 32 bit organization (Double Word mode: W = VIH) • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) • Supply current: – Operating: 180 mA (MAX.) – Standby: 300 µA (MAX.) • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Static operation • Package: 70-pin, 500-mil SSOP • Others: – Non programmable – Not designed or rated as radiation – hardened – CMOS process (P type silicon .

  LH53B16R00   LH53B16R00



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LH53B16R00 FEATURES • 1,048,576 × 16 bit organization (Word mode: W = VIL) 524,288 × 32 bit organization (Double Word mode: W = VIH) • Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) • Supply current: – Operating: 180 mA (MAX.) – Standby: 300 µA (MAX.) • TTL compatible I/O • Three-state outputs • Single +5 V power supply • Static operation • Package: 70-pin, 500-mil SSOP • Others: – Non programmable – Not designed or rated as radiation – hardened – CMOS process (P type silicon substrate) DESCRIPTION The LH53B16R00 is a 16M-bit CMOS mask ROM (mask-programmable-read-only memory) organized as 1,048,576 × 16 bits (Word mode) or 524,288 × 32 bits (Double Word mode). It is fabricated using silicon-gate CMOS process technology. CMOS 16M (1M × 16/512K × 32) MROM PIN CONNECTIONS 70-PIN SSOP A0 A1 A2 A3 A4 A5 VCC D0 D16 D1 D17 GND VCC D2 D18 D3 D19 D4 D20 D5 D21 GND VCC D6 D22 D7 D23 GND A6 A7 A8 A9 A10 A11 A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 NC NC NC W OE CE GND D31/A-1 (NOTE) D15 D30 D14 GND VCC D29 D13 D28 D12 D27 D11 D26 D10 GND VCC D25 D9 D24 D8 VCC NC A18 A17 A16 A15 A14 A13 TOP VIEW NOTE: D31/A-1 pin becomes LSB address input (A-1) when the W pin is set to be LOW in word mode, and data output (D31) when set to be HIGH in double word mode. 53B16R00-1 Figure 1. Pin Connections 1 LH53B16R00 CMOS 16M (1M x 16/512K x 32) MROM 63 D31 61 D30 57 D29 55 D28 53 D27 51 D26 A18 41 A17 40 A16 39 A15 38 A14 37 MEMORY MATRIX (1,048,576 x 16) (524,288 x 32) 47 45 27 25 21 19 17 15 11 9 62 60 56 54 52 50 46 44 26 24 20 18 16 14 10 8 D25 D24 D23 D22 D21 D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 A9 A8 A7 A6 32 31 30 29 ADDRESS BUFFER A13 36 A12 35 A11 34 A10 33 A5 6 A4 5 A3 4 A2 3 COLUMN SELECTOR CE 65 CE BUFFER TIMING GENERATOR SENSE AMPLIFIER OE 66 OE BUFFER 12 22 DATA SELECTOR/OUTPUT BUFFER ADDRESS DECODER W 67 WORD/DOUBLE WORD SWITCHOVER CIRCUIT ADDRESS BUFFER ADDRESS BUFFER 28 49 59 64 GND 63 A-1 1 A0 2 A1 7 13 23 43 48 58 VCC 53B16R00-2 Figure 2. LH53B16R00 Block Diagram 2 CMOS 16M (1M x 16/512K x 32) MROM LH53B16R00 PIN DESCRIPTION SIGNAL PIN NAME SIGNAL PIN NAME A-1 - A1 A2 - A18 D0 - D31 W Address input (page mode operation) Address input Data output ×16 bit / ×32 bit (word/double word) mode select input CE OE VCC GND NC Chip enable input Output enable input Power pin (+5 V) Ground No connection TRUTH TABLE CE OE W A-1 (D31) DATA OUTPUT D0 - D15 D16 - D31 ADDRESS INPUT LSB MSB SUPPLY CURRENT H L L L L X H L L L X X H L L X X  L H High-Z High-Z D0 - D15 D0 - D15 D16 - D31 High-Z High-Z D16 - D31 High-Z High-Z   A0 A-1 A-1   A18 A18 A18 Standby (ISB) Operating Operating Operating Operating NOTE: X = Don’t care; High-Z = High-impedance ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING UNIT Supply voltage Input voltage Output voltage Operating temperature Storage temperature VCC VIN VOUT TOPR TSTG -0.3 to +7.0 -0.3 to VCC + 0.3 -0.3 to VCC + 0.3 0 to +70 -65 to +150 V V V °C °C RECOMMENDED OPERATING CONDITIONS (TA = 0 to +70°C) PARAMETER SYMBOL MIN. TYP. MAX. UNIT Supply voltage VCC 4.5 5.0 5.5 V 3 LH53B16R00 CMOS 16M (1M x 16/512K x 32) MROM DC ELECTRICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL CONDITIONS MIN. MAX. UNIT NOTE Input ‘High’ voltage Input ‘Low’ voltage Output ‘High’ voltage Output ‘Low’ voltage Input leakage current Output leakage current Operating current Standby current Input capacitance Output capacitance V IH VIL VOH VOL | ILI | | ILO | ICC1 ISB1 ISB2 CIN COUT   I OH = -400 µ A I OL = 2.0 mA V IN = 0 V to VCC V OUT = 0 V to VCC t RC = 120 ns CE = VIH CE = VCC - 0.2 V f = 1 MHz, t A = 25° C 2.2 -0.3 2.4         VCC +0.3 0.8  0.4 10 10 180 2 300 10 10 V V V V µA µA mA mA µA pF pF      1 2     NOTES: 1. CE = VIH, OE = VIH, output is open 2. VIN = VIH, VIL, CE = VIL, output is open AC ELECTRICAL CHARACTERISTICS (VCC = 5 V ±10%, TA = 0 to +70°C) PARAMETER SYMBOL MIN. MAX. UNIT NOTE Read cycle time Address access time Chip enable access time Page address access time Output enable delay time Output hold time Output floating time tRC tAA tACE tAPA tOE tOH tCHZ tOHZ 120     5    120 120 50 50  40 40 ns ns ns ns ns ns ns ns      1 NOTE: 1. Determined by the time for the output to be opened. (Irrespective of output voltage) AC TEST CONDITIONS PARAMETER RATING Input voltage amplitude Input signal rise time Input signal fall time Input/output reference level Output load condition 0.4 V to 2.6 V 10 ns 10 ns 1.5 V 1TTL + 100 pF 4 CMOS 16M (1M x 16/512K x 32) MROM LH53B16R00 tRC A-1 - A18 (A0 - A18) tAA (NOTE) CE tACE (NOTE) OE tOE (NOTE) tOHZ tOH tCHZ D0 - D15 (D0 - D31) NOTE: The output data becomes valid when the last intervals, tAA, tACE, tAPA, or tOE.


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