LH540204

LH540204 FEATURES Fast Access Times: 20/25/35/50 ns Fast-Fall-Through Time Architecture Based on CMOS Dual-Port SRAM Technology Input Port and Output Port Have Entirely Independent Timing Expandable in Width and Depth Full, Half-Full, and Empty Status Flags Data Retransmission Capability TTL-Compatible I/O Pin and Functionally Compatible with Sharp LH5499 and with Am/IDT/MS7204 Control Signals Assertive-LOW for Noise Immunity Packages: 28-Pin, 300-mil PDIP 28-Pin, 300-mil SOJ * 32-Pin PLCC CMOS 4096 × 9 Asynchronous FIFO FUNCTIONAL DESCRIPTION The LH540204 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS dual-port SRAM technology, capable of storing up to 4096 nine-bit words. It follows the industry-standard architecture and package pinouts for nine-bit asynchronous FIFOs. Each nine-bit LH540204 word may consist of a standard eight-bit byte, together with a parity bit or a block-marking/framing bit. The input and output ports operate entirely independently of each other, unless the LH540204 becomes either totally full or else totally empty. Data flow at a port is initiated by asserting either of two asynchronous, assertive-LOW control inputs: Write (W) for data entry at the input port, or Read (R) for data retrieval at the output port. Full, Half-Full, and Empty status flags monitor the extent to which the internal memory has been filled. The system may make use of these status outputs to avoid the risk of data loss, which otherwi...