LH540215

LH540215/25 FEATURES Fast Cycle Times: 20/25/35 ns Pin-Compatible Drop-In Replacements for IDT72215B/25B FIFOs 512 × 18 / 1024 × 18 Synchronous FIFO May be Cascaded for Increased Depth, or Paralleled for Increased Width Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty; ‘Almost’ Flags are Programmable Choice of IDT-Compatible or Enhanced Operating Mode; Selected by an Input Control Signal In Enhanced Operating Mode, Almost-Full, Half-Full, and Almost-Empty Flags can be Made Completely Synchronous Device Comes Up into One of Two Known Default States at Reset Depending on the State of the EMODE Control Input: Programming is Allowed, but is not Required In Enhanced Operating Mode, Duplicate Enables for Interlocked Paralleled FIFO Operation, for 36-Bit Data Width, when Selected and Appropriately Connected Internal Memory Array Architecture Based on CMOS Dual-Port SRAM Technology, 512 × 18 or 1024 × 18 Input Port and Output Port ‘Synchronous’ Enable-Plus-Clock Control at Both Independently-Synchronized Operation of Input Port and Output Port In Enhanced Operating Mode, Disabling Three-State Outputs May be Made to Suppress Reading Control Inputs Sampled on Rising Clock Edge Most Control Signals Assertive-LOW for Noise Immunity Data Retransmit Function TTL/CMOS-Compatible I/O Space-Saving 68-Pin PLCC Package, and 64-Pin TQFP Package RS RESET LOGIC FL/RT WXI/WEN2 WXO/HF RXI/REN2 RXO/EF2 EXPANSION LOGIC FIFO MEMO...