Document
FUJITSU MICROELECTRONICS DATA SHEET
DS07-13707-3Ea
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90520A/520B Series
www.DataSheet4U.com
MB90522A/523A/522B/523B/F523B/V520A
■ DESCRIPTION
The MB90520A/520B series is a general-purpose 16-bit microcontroller designed for process control applications in consumer products that require high-speed real-time processing. The microcontroller instruction set is based on the AT architecture of the F2MC* family with additional instructions for high-level languages, extended addressing modes, enhanced multiplication and division instructions, and a complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word (32-bit) data. The MB90520A/520B series peripheral resources include an 8/10-bit A/D converter, 8-bit D/A converter, UART (SCI) , extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and 1, a range of I/O timers (16-bit free-run timers 1 and 2, input capture (ICU) 0 and 1, and output compare (OCU) 0 and 1) , an LCD controller/driver, 8 external interrupt inputs, and 8 wakeup interrupts.
* : F2MC stands for FUJITSU Flexible MicroController.
■ FEATURES
• Clock • Internal PLL clock multiplication circuit • Selectable machine clock (PLL clock) : Base oscillation divided by two or multiplied by one to four (For a 4 MHz base oscillation, the machine clock range is 4 MHz to 16 MHz) . (Continued)
■ PACKAGES
120-pin, Plastic, LQFP 120-pin, Plastic, QFP
(FPT-120P-M05)
(FPT-120P-M13)
Copyright©2002-2008 FUJITSU MICROELECTRONICS LIMITED All rights reserved 2002.3
MB90520A/520B Series
(Continued) • Sub-clock (32.768 KHz) operation available Minimum instruction execution time : 62.5 ns (for oscillation = 4 MHz, PLL clock setting = ×4, VCC = 5.0 V) • 16MB CPU memory space Internal 24-bit addressing • Instruction set optimized for controller applications Rich data types (bit, byte, word, long-word) Extended addressing modes (23 types) Enhanced signed multiplication and division instructions and RETI instruction Enhanced calculation precision using a 32-bit accumulator • Instruction set designed for high-level language (C) and multi-tasking www.DataSheet4U.com System stack pointer Enhanced pointer-indirect instructions and barrel shift instructions • Faster execution speed 4-byte instruction queue ROM mirror function (48 Kbytes of bank FF is mirrored in bank 00) • Program patch function : An address match detection function (2 × addresses) • Interrupt function 32 programmable interrupts with 8 levels • Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS) : Up to 16 channels • Low-power consumption (stand-by) modes Sleep mode (CPU operating clock stops, peripherals continue to operate.) Pseudo-clock mode (Only oscillation clock and timebase timer continue to operate.) Clock mode (Main oscillation clock stops, sub-clock and clock timer conti.