LH543620

LH543620 FEATURES Fast Cycle Times: 20/25/30 ns Selectable 36/18/9-Bit Word Width for Both Input Port and Output Port Byte-Order-Reversal Function (i.e., ‘Big-Endian’ £ ‘Little-Endian’ Conversion) 16-mA-IOL Three-State Outputs Automatic Byte Parity Checking Selectable Byte Parity Generation Five Status Flags: Full, Almost-Full, Half-Full, Almost-Empty, and Empty All FIFO Status Flags are Synchronous (AE, HF, AF Through Programming of Control Register) Programmed Values may be entered from either Port Two Enable Control Signals for each Port Mailbox Register with Synchronized Flags Asynchronous Data-Bypass Function ‘Smart’ Data-Retransmit Function Configurable for Paralleled FIFO Operation (72-Bit Data Width) Space-Saving PQFP and TQFP Packages 1 1024 × 36 Synchronous FIFO FUNCTIONAL DESCRIPTION The LH543620 is a FIFO (First-In, First-Out) memory device, based on fully-static CMOS RAM technology, capable of containing up to 1024 36-bit words. It can replace four or more nine-bit-wide FIFOs in many applications. The input port and the output port operate independently of each other. Write operations are performed on the rising edge of the input clock CKI, and enabled by two enabled signals ENI1, ENI2. Read operations are performed on the rising edge of the output clock CKO and enabled by two enabled signals ENO1, ENO2. Five status flags are available to monitor the memory array status: Full, Almost-Full, Half-Full, Almost-Empty, and Empty. The Alm...