Document
FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13704-3E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90590/590G Series
www.DataSheet4U.com
MB90591/F591A/594/594G/F594A/F594G MB90V590A/V590G
s DESCRIPTION
The MB90590/590G series with two FULL-CAN*1 interfaces and FLASH ROM is especially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal full CAN approach. The instruction set of F2MC-16LX CPU core inherits an AT architecture of the F2MC*2 family with additional instruction sets for high-level languages, extended addressing mode, enhanced multiplication/division instructions, and enhanced bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long word data. The MB90590/590G series has peripheral resources of 8/10-bit A/D converters, UART (SCI), extended I/O serial interface, 8/16-bit PPG timer, I/O timer (input capture (ICU), output compare (OCU)), stepping motor controller, and sound generator. *1: Controller Area Network (CAN) - License of Robert Bosch GmbH *2: F2MC stands for FUJITSU Flexible Microcontroller.
s FEATURES
• Clock Embedded PLL clock multiplication circuit Operating clock (PLL clock) can be selected from divided-by-2 of oscillation or one to four times the oscillation (at oscillation of 4 MHz, 4 MHz to 16 MHz). Minimum instruction execution time: 62.5 ns (operation at oscillation of 4 MHz, four times the oscillation clock, VCC of 5.0 V) (Continued)
s PACKAGE
100-pin Plastic QFP
(FPT-100P-M06)
MB90590/590G Series
(Continued) • Instruction set to optimize controller applications Rich data types (bit, byte, word, long word) Rich addressing mode (23 types) Enhanced signed multiplication/division instruction and RETI instruction functions Enhanced precision calculation realized by the 32-bit accumulator • Instruction set designed for high level language (C language) and multi-task operations Adoption of system stack pointer Enhanced pointer indirect instructions Barrel shift instructions • Program patch function (for two address pointers) www.DataSheet4U.com • Enhanced execution speed: 4-byte instruction queue • Enhanced interrupt function: 8 levels, 34 factors • Automatic data transmission function independent of CPU operation Extended intelligent I/O service function (EI2OS): Up to 10 channels • Embedded ROM size and types Mask ROM: 256 Kbytes/384 Kbytes Flash ROM: 256 Kbytes/384 Kbytes Embedded RAM size: 6 Kbytes/8 Kbytes • Flash ROM Supports automatic programming, Embedded Algorithm TM∗ Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Hard-wired reset vector available in order to point to a fixed boot sector in Flash Memory Erase can be performed on each block Block protection with external programming voltage • Low-power consumption (stand-by) mode Sleep mode (mode in which CPU operating clock is stopped) Stop mode (mode in which oscillation is stopped) CPU intermittent operation mode Clock mode Hardware stand-by mode • Process 0.5µm CMOS technology • I/O port General-purpose I/O ports: 78 ports • Timer Watchdog timer: 1 channel 8/16-bit PPG timer: 8/16-bit × 6 channels 16-bit re-load timer: 2 channels • 16-bit I/O timer 16-bit free-run timer: 1 channel Input capture: 6 channels Output compare: 6 channels • Extended I/O serial interface: 1 channel • UART (3 channels) With full-duplex double buffer (8-bit length) Clock asynchronized or clock synchronized (with start/stop bit) transmission can be selectively used. • Stepping motor controller (4 channels)
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MB90590/590G Series
• External interrupt circuit (8 channels) A module for starting an extended intelligent I/O service (EI2OS) and generating an external interrupt which is triggered by an external input. • Delayed interrupt generation module Generates an interrupt request for switching tasks. • 8/10-bit A/D converter (8 channels) 8/10-bit resolution can be selectively used. Starting by an external trigger input. • FULL-CAN interfaces: 2 Conforming to Version 2.0 Part A and Part B www.DataSheet4U.com Flexible message buffering (mailbox and FIFO buffering can be mixed) • Sound generator • 18-bit Time-base counter • Clock timer: 1 channel • External bus interface: Maximum address space 16 Mbytes *: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
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MB90590/590G Series
s PRODUCT LINEUP
Features Classification ROM size RAM size Emulator-specific power supply *1 www.DataSheet4U.com MB90591/594/594G Mask ROM product 384/256 Kbytes 8/6 Kbytes MB90F591A/F594A/F594G Flash ROM product 384/256 Kbytes Boot block Hard-wired reset vector 8/6 Kbytes MB90V590A/V590G Evaluation product None 8 Kbytes None
CPU functions
The number of instructions: 340 Instruction bit length: 8 bits, 16 bits Instruction length: 1 byte to 7 bytes Data bit length: 1 bit, 8 bits, 16 bits .