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MS8104166A Dataheets PDF



Part Number MS8104166A
Manufacturers OKI electronic componets
Logo OKI electronic componets
Description Dual FIFO
Datasheet MS8104166A DatasheetMS8104166A Datasheet (PDF)

OKI Semiconductor MS8104166A Dual FIFO (262,214 Words × 8 Bits) × 2 FEDS8104166A-01 This version: Nov.,21, 2002 GENERAL DESCRIPTION The MS8104166A is a single-chip 4Mb FIFO functionally composed of two Oki’s 2Mb FIFO (First-In First-Out) memories which were designed for 256k × 8-bit high-speed asynchronous read/write operation. www.DataSheet4U.com The read clock of each of the 2Mb FIFO memories is connected in common, and the clocks are provided independently of each of the FIFO memories. The .

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OKI Semiconductor MS8104166A Dual FIFO (262,214 Words × 8 Bits) × 2 FEDS8104166A-01 This version: Nov.,21, 2002 GENERAL DESCRIPTION The MS8104166A is a single-chip 4Mb FIFO functionally composed of two Oki’s 2Mb FIFO (First-In First-Out) memories which were designed for 256k × 8-bit high-speed asynchronous read/write operation. www.DataSheet4U.com The read clock of each of the 2Mb FIFO memories is connected in common, and the clocks are provided independently of each of the FIFO memories. The MS8104166A functionally compatible with Oki’s 2Mb FIFO memory (MSM518222A), can be used as a ×16 configuration FIFO. The MS8104166A is a field memory for wide or low end use in general commodity TVs and VTRs exclusively and is not designed for high end use in professional graphics systems, which require long term picture storage, data storage, medical use and other storage systems. The MS8104166A provides independent control clocks to support asynchronous read and write operations. Different clock rates are also supported, which allow alternate data rates between write and read data streams. The MS8104166A provides high speed FIFO (First-in First-out) operation without external refreshing: MS8104166A refreshes its DRAM storage cells automatically, so that it appears fully static to the users. Moreover, fully static type memory cells and decoders for serial access enable the refresh free serial access operation, so that serial read and/or write control clock can be halted high or low for any duration as long as the power is on. Internal conflicts of memory access and refreshing operations are prevented by special arbitration logic. The MS8104166A’s function is simple, and similar to a digital delay device whose delay-bit-length is easily set by reset timing. The delay length and the number of read delay clocks between write and read, is determined by externally controlled write and read reset timings. Additional SRAM serial registers, or line buffers for the initial access of 71 × 16-bit enable high speed first-bit-access with no clock delay just after the write or read reset timings. The MS8104166A, which is provided with two sets of the serial write clocks, allows the split-screen processing to be implemented easily. Additionally, the MS8104166A has a write mask function or input enable function (IE), and read-data skipping function or output enable function (OE). The differences between write enable (WE) and input enable (IE), and between read enable (RE) and output enable (OE) are that WE and RE can stop serial write/read address increments, but IE and OE cannot stop the increment, when write/read clocking is continuously applied to the MS8104166A. The input enable (IE) function allows the user to write into selected locations of the memory only, leaving the rest of the memory contents unchanged. This facilitates data processing to display a “picture in picture” on a TV screen. 1/19 FEDS8104166A-01 1 Semiconductor MS8104166A FEATURES 262,214 words × 8 bits × 2 Fast FIFO (First-In First-Out) Operation: 25 ns cycle time Self refresh (No refresh control is required) High speed asynchronous serial access Read/Write Cycle Time 20 ns/25 ns Access Time 18 ns/22 ns www.DataSheet4U.com • Variable length delay bit (150 to 262214) • Write mask function (Output enable control) • Cascading capability by mode setting • Single power supply: 5.0 V ± 0.5V • Package: 100-Pin plastic TQFP (TQFP 100-P-1414-0.50-k) (Product: MS8104166A-xxTB) xx indicates speed rank. • • • • Parameter Access Time Read/Write Cycle Time Operation current Standby current Symbol tAC tSWC tSRC ICC1 ICC2 MS8104166A-xxTB –20 18 ns 20 ns 170 mA 5 mA –25 22 ns 25 ns 170 mA 5 mA 2/19 FEDS8104166A-01 1 Semiconductor MS8104166A PIN CONFIGURATION (TOP VIEW) NC DI22 DI21 DI20 RSTW2 IE2 WE2 VSS VCC VSS NC VCC NC VSS NC MODE1 NC VCC RSTR2 RE2 OE2 NC VSS VSS NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 www.DataSheet4U.com NC DI23 VSS DI24 DI25 DI26 DI27 NC VSS VSS VCC VCC SWCK2 VCC VCC VSS VSS NC DI17 DI16 DI15 DI14 VSS DI13 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 PIN TQFP TOP VIEW 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VCC DO20 DO21 VSS DO22 DO23 DO24 DO25 VSS DO26 DO27 VCC SRCK VCC DO17 DO16 VSS DO15 DO14 DO13 DO12 VSS DO11 DO10 VCC Pin Name SWCK1 SWCK2 WE1 RE1 IE1 OE1 RSTW1 RSTR1 DI10 to 17 DO10 to 17 MODE1 VCC NC DI12 DI11 DI10 RSTW1 IE1 WE1 VSS VCC VSS NC VCC NC VSS NC SWCK1 NC VCC RSTR1 RE1 OE1 NC VSS VSS NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Function Port1 Serial Write clock Port2 Serial Write clock Port1 Write Enable Port1 Read Enable Port1 Input Enable Port1 Output Enable Port1 Reset Write Port1 Reset Read Port1 Data Input Port1 Data Output Mode Input Power Supply (5.0 V) Pin Name SRCK WE2 RE2 IE2 OE2 RSTW2 RSTR2 DI20 to 27 DO20 to 27 NC VSS Function Serial Read Clock Port2 Write Enable Port2 Re.


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