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LH5491

Sharp Electrionic Components

Cascadable 64 x 8 FIFO Cascadable 64 x 9 FIFO

LH5481 LH5491 FEATURES • Fastest 64 × 8/9 Cascadable FIFO 35/25/15 MHz • Expandable in Word Width and FIFO Depth • Almos...


Sharp Electrionic Components

LH5491

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Description
LH5481 LH5491 FEATURES Fastest 64 × 8/9 Cascadable FIFO 35/25/15 MHz Expandable in Word Width and FIFO Depth Almost-Full/Almost-Empty and Half-Full Flags Fully Independent Asynchronous Inputs and Outputs LH5481 Output Enable forces Data Outputs to High-Impedance State Pin-Compatible Replacements for Cypress CY7C408A/09A or Logic Devices L8C408/09 FIFOs Industry Standard Pinout Packages: 28-Pin, 300-mil DIP 28-Pin PLCC FUNCTIONAL DESCRIPTION The LH5481 and LH5491 are high-performance, asynchronous First-In, First-Out (FIFO) memories organized 64 words deep by eight or nine bits wide. The eight-bit LH5481 has an Output Enable (OE) function, which can be used to force the eight data outputs (DO) to a high-impedance state. The LH5491 has nine data outputs. These FIFOs accept eight or nine-bit data at the Data Inputs (DI). A Shift In (SI) signal writes the DI data into the FIFO. A Shift Out (SO) signal shifts stored data to the Data Outputs (DO). The Output Ready (OR) signal indicates when valid data is present on the DO outputs. If the FIFO is full and unable to accept more DI data, Input Ready (IR) will not return HIGH, and SI pulses will be ignored. If the FIFO is empty and unable to shift data to the DO outputs, OR will not return HIGH, and SO pulses will be ignored. The Almost-Full/Almost-Empty (AFE) flag is asserted (HIGH) when the FIFO is almost-full (56 words or more) or almost- empty (eight words or less). Cascadable 64 × 8 FIFO Cascadable 64 × 9 FIFO The...




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