LH5P864

LH5P864 FEATURES 65,536 × 8 bit organization Access time: 80 ns (MAX.) Cycle time: 140 ns (MIN.) Single +5 V power supply Power consumption: Operating: 440 mW (MAX.) Standby (TTL level): 22 mW (MAX.) Standby (CMOS level): 2.75 mW (MAX.) Operating temperature: 0 to 70°C TTL compatible I/O 512 refresh cycles/8 ms (MAX.) Available for auto-refresh and self-refresh modes Package: 32-pin, 525-mil SOP DESCRIPTION The LH5P864 is a 512K-bit Pseudo-Static RAM organized as 65,536 × 8 bits. It is fabricated using silicon-gate CMOS process technology. With its built-in oscillator, it is easy to refresh memories without an external clock. CMOS 512K (64K × 8) Pseudo-Static RAM PIN CONNECTIONS 32-PIN SOP TOP VIEW TEST NC A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC NC CE2 R/W A13 A8 A9 A11 OE/RFSH A10 CE1 I/O7 I/O6 I/O5 I/O4 I/O3 5P864-1 Figure 1. Pin Connections for SOP Package 1 LH5P864 CMOS 512K (64K × 8) Pseudo-Static RAM 16 GND 32 VCC A0 12 A1 11 A2 10 A3 9 A4 8 A5 7 A6 A7 A8 A9 6 5 27 26 A0 - A7 ROW ADDRESS BUFFER SENSE AMPS I/O SELECTOR DATA IN BUFFER 13 I/O0 14 I/O1 15 I/O2 17 I/O3 18 I/O4 19 I/O5 20 I/O6 DATA OUT BUFFER 21 I/O7 VBB GENERATOR A8 - A14 COLUMN ADDRESS BUFFER COLUMN DECODER A10 23 A11 25 A12 4 A13 28 A14 3 REFRESH ADDRESS COUNTER EXT/INT ADDRESS MUX ROW DECODER MEMORY ARRAY 256K MEMORY ARRAY 256K CE1 22 CE2 30 CLOCK GENERATOR TEST1 ...