AD9273 Switch Datasheet

AD9273 Datasheet PDF, Equivalent


Part Number

AD9273

Description

Octal LNA/VGA/AAF/ADC and Crosspoint Switch

Manufacture

Analog Devices

Total Page 30 Pages
PDF Download
Download AD9273 Datasheet PDF


AD9273
FEATURES
8 channels of LNA, VGA, AAF, and ADC
Low noise preamplifier (LNA)
Input-referred noise voltage = 1.26 nV/√Hz
(gain = 21.3 dB) @ 5 MHz typical
SPI-programmable gain = 15.6 dB/17.9 dB/21.3 dB
Single-ended input; VIN maximum = 733 mV p-p/
550 mV p-p/367 mV p-p
Dual-mode active input impedance matching
Bandwidth (BW) > 100 MHz
Full-scale (FS) output = 4.4 V p-p differential
Variable gain amplifier (VGA)
Attenuator range = −42 dB to 0 dB
SPI-programmable PGA gain = 21 dB/24 dB/27 dB/30 dB
Linear-in-dB gain control
Antialiasing filter (AAF)
Programmable 2nd-order low-pass filter (LPF) from
8 MHz to 18 MHz
Programmable high-pass filter (HPF)
Analog-to-digital converter (ADC)
12 bits at 10 MSPS to 50 MSPS
SNR = 70 dB
SFDR = 75 dB
Serial LVDS (ANSI-644, IEEE 1596.3 reduced range link)
Data and frame clock outputs
Includes an 8 × 8 differential crosspoint switch to support
continuous wave (CW) Doppler
Low power, 109 mW per channel at 12 bits/40 MSPS (TGC)
70 mW per channel in CW Doppler
Flexible power-down modes
Overload recovery in <10 ns
Fast recovery from low power standby mode, <2 μs
100-lead TQFP and 144-ball BGA
APPLICATIONS
Medical imaging/ultrasound
Automotive radar
GENERAL DESCRIPTION
The AD9273 is designed for low cost, low power, small size, and
ease of use. It contains eight channels of a low noise preamplifier
(LNA) with a variable gain amplifier (VGA); an antialiasing
filter (AAF); and a 12-bit, 10 MSPS to 50 MSPS analog-to-
digital converter (ADC).
Each channel features a variable gain range of 42 dB, a fully
differential signal path, an active input preamplifier termination, a
maximum gain of up to 52 dB, and an ADC with a conversion
rate of up to 50 MSPS. The channel is optimized for dynamic
performance and low power in applications where a small
package size is critical.
Octal LNA/VGA/AAF/ADC
and Crosspoint Switch
AD9273
FUNCTIONAL BLOCK DIAGRAM
LOSW-A
LO-A
LI-A
LNA VGA
LG-A
LOSW-B
LO-B
LI-B
LG-B LNA VGA
LOSW-C
LO-C
LI-C
LG-C LNA VGA
LOSW-D
LO-D
LI-D LNA VGA
LG-D
LOSW-E
LO-E
LI-E
LG-E LNA VGA
LOSW-F
LO-F
LI-F
LG-F LNA VGA
LOSW-G
LO-G
LI-G
LNA VGA
LG-G
LOSW-H
LO-H
LI-H
LG-H LNA VGA
SWITCH
ARRAY
AD9273
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTA+
DOUTA–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTB+
DOUTB–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTC+
DOUTC–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTD+
DOUTD–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTE+
DOUTE–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTF+
DOUTF–
AAF
12-BIT
ADC
SERIAL
LVDS
DOUTG+
DOUTG–
AAF
12-BIT
ADC
REFERENCE
SERIAL
LVDS
DOUTH+
DOUTH–
FCO+
FCO–
DCO+
DCO–
Figure 1.
The LNA has a single-ended-to-differential gain that is selectable
through the SPI. The LNA input-referred noise voltage is typically
1.26 nV/√Hz at a gain of 21.3 dB, and the combined input-referred
noise voltage of the entire channel is 1.42 nV/√Hz at typical
gain. Assuming a 15 MHz noise bandwidth (NBW) and a 21.3 dB
LNA gain, the input SNR is about 91 dB. In CW Doppler mode,
the LNA output drives a transconductance amp that is switched
through an 8 × 8 differential crosspoint switch. The switch is
programmable through the SPI.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.

AD9273
AD9273* Product Page Quick Links
Last Content Update: 11/01/2016
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Evaluation Kits
• AD9273 Evaluation Board
Documentation
Application Notes
• AN-1142: Techniques for High Speed ADC PCB Layout
• AN-586: LVDS Outputs for High Speed A/D Converters
• AN-737: How ADIsimADC Models an ADC
• AN-812: MicroController-Based Serial Port Interface (SPI)
Boot Circuit
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• AN-877: Interfacing to High Speed ADCs via SPI
• AN-878: High Speed ADC SPI Control Software
• AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
• AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
• AD9273: Octal LNA/VGA/AAF/ADC and Crosspoint
Switch Data Sheet
Software and Systems Requirements
• UG-001: Evaluation Board User Guide
Tools and Simulations
• Visual Analog
• AD9273 IBIS Models
Reference Materials
Press
• Industry’s First Octal Ultrasound Receiver with Digital I/Q
Demodulator and Decimation Filter Reduces Processor
Overhead in Ultrasound Systems
• Low Cost, Octal Ultrasound Receiver with On-Chip RF
Decimator and JESD204B Serial Interface
Technical Articles
• MS-2210: Designing Power Supplies for High Speed ADC
• New Components Offer Fexibility in Ultrasound System
Design
• Processors for Ultrasound Improve Image Quality
Design Resources
• AD9273 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
Discussions
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Technical Support
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Features FEATURES 8 channels of LNA, VGA, AAF, an d ADC Low noise preamplifier (LNA) Inpu t-referred noise voltage = 1.26 nV/√H z (gain = 21.3 dB) @ 5 MHz typical SPI- programmable gain = 15.6 dB/17.9 dB/21. 3 dB Single-ended input; VIN maximum = 733 mV p-p/ 550 mV p-p/367 mV p-p Dual- mode active input impedance matching Ba ndwidth (BW) > 100 MHz Full-scale (FS) output = 4.4 V p-p differential Variabl e gain amplifier (VGA) Attenuator range = −42 dB to 0 dB SPI-programmable PG A gain = 21 dB/24 dB/27 dB/30 dB Linear -in-dB gain control Antialiasing filter (AAF) Programmable 2nd-order low-pass filter (LPF) from 8 MHz to 18 MHz Progr ammable high-pass filter (HPF) Analog-t o-digital converter (ADC) 12 bits at 10 MSPS to 50 MSPS SNR = 70 dB SFDR = 75 dB Serial LVDS (ANSI-644, IEEE 1596.3 r educed range link) Data and frame clock outputs Includes an 8 × 8 differentia l crosspoint switch to support continuo us wave (CW) Doppler Low power, 109 mW per channel at 12 bits/40 MSPS (TGC) 70 mW per channel in CW Doppler.
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