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Freescale Semiconductor Hardware Specification
MCF5271EC Rev. 1.2, 12/2004
MCF5271 Integrated Microprocessor Hardware Specification
32-bit Embedded Controller Division
The MCF5271 family is a highly integrated implementation of the ColdFire® family of reduced instruction set computing (RISC) microprocessors. This document describes pertinent features and functions of the MCF5271 family. The MCF5271 family includes the MCF5271 and MCF5270 microprocessors. The differences between these parts are summarized below in Table 1. This document is written from the perspective of the MCF5271 and unless otherwise noted, the information applies also to the MCF5270. The MCF5271 family combines low cost with high integration on the popular version 2 ColdFire core with over 96 (Dhrystone 2.1) MIPS at 100MHz. Positioned for applications requiring a cost-sensitive 32-bit solution, the MCF5271 family features a 10/100 Ethernet MAC and optional hardware encryption to ensure the application can be connected and protected. In addition, the MCF5271 family features an enhanced Multiply Accumulate Unit (eMAC), large on-chip memory (64 Kbytes SRAM, 8 Kbytes configurable cache), and a 32-bit SDR SDRAM memory controller.
Table of Contents
1 2 3 4 5 6 7 8 9 MCF5271 Family Configurations ..................... 2 Block Diagram ................................................. 2 Features .......................................................... 4 Signal Descriptions........................................ 12 Modes of Operation....................................... 16 Design Recommendations ............................ 19 Mechanicals/Pinouts and Part Numbers ....... 27 Preliminary Electrical Characteristics............ 32 Documentation .............................................. 55
Technical Data © Freescale Semiconductor, Inc., 2004. All rights reserved.
MCF5271 Family Configurations
1
MCF5271 Family Configurations
Table 1. MCF5271 Family Configurations
Module ColdFire V2 Core with EMAC and Hardware Divide System Clock Performance (Dhrystone/2.1 MIPS) Instruction/Data Cache Static RAM (SRAM) Interrupt Controllers (INTC) Edge Port Module (EPORT) External Interface Module (EIM) 4-channel Direct-Memory Access (DMA) SDRAM Controller Fast Ethernet Controller (FEC) Hardware Encryption Watchdog Timer (WDT) Four Periodic Interrupt Timers (PIT) 32-bit DMA Timers QSPI UART(s) I2C General Purpose I/O Module (GPIO) JTAG - IEEE 1149.1 Test Access Port Package
2 x x x x x — x x 4 x 3 x x x
5270
x
5271
x
100 MHz 96 8 Kbytes 64 Kbytes 2 x x x x x x x x 4 x 3 x x x
160 QFP, 160 QFP, 196 MAPBGA 196 MAPBGA
2
Block Diagram
The superset device in the MCF5271 family comes in a 196 mold array plastic ball grid array (MAPBGA) package. Figure 1 shows a top-level block diagram of the MCF5271.
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 2 Freescale Semiconductor
Block Diagram
SDRAMC QSPI
EIM (To/From SRAM backdoor) CHIP SELECTS
I2C_SDA I2C_SCL UnTXD UnRXD UnRTS
EBI Arbiter INTC0 INTC1 PADI – Pin Muxing
UnCTS TnOUT TnIN FEC
(To/From PADI)
FAST ETHERNET CONTROLLER (FEC)
UART 0
UART 1
UART 2
I2 C
QSPI
SDRAMC
D[31:0]
(To/From PADI) (To/From PADI)
4 CH DMA
DTIM 0
DTIM 1
DTIM 2
DTIM 3
A[23:0] R/W CS[3:0] TA
DREQ[2:0] DACK[2:0]
MUX
TSIZ[1:0]
BDM
JTAG_EN
V2 ColdFire CPU
DIV EMAC
TEA BS[3:0]
JTAG TAP 64 Kbytes SRAM (8Kx16)x4 8 Kbytes CACHE (1Kx32)x2 PORTS (GPIO)
CIM
Watchdog Timer
(To/From Arbiter)
SKHA
PLL CLKGEN (To/From INTC)
PIT0
PIT1
PIT2
PIT3
RNGA
MDHA Cryptography Modules
Edge Port
Figure 1. MCF5271 Block Diagram
MCF5271 Integrated Microprocessor Hardware Specification, Rev. 1.2 Freescale Semiconductor 3
Features
3
Features
This document contains information on a new product. Specifications and information herein are subject to change without notice.
3.1
•
Feature Overview
Version 2 ColdFire variable-length RISC processor core — Static operation — 32-bit address and data path on-chip — Processor core runs at twice the bus frequency — Sixteen general-purpose 32-bit data and address registers — Implements the ColdFire Instruction Set Architecture, ISA_A, with extensions to support the user stack pointer register, and 4 new instructions for improved bit processing — Enhanced Multiply-Accumulate (EMAC) unit with four 48-bit accumulators to support 32-bit signal processing algorithms — Illegal instruction decode that allows for 68K emulation support System debug support — Real time trace for determining dynamic execution path — Background debug mode (BDM) for in-circuit debugging — Real time debug support, with two user-visible hardware breakpoint registers (PC and address with optional data) that can be configured into a 1- or 2-level trigger On-chip memories — 8-Kbyte cache, configurable as instruction-only, data-only, or split I-/D-cache — 64-Kbyte dual-ported SRAM on CPU internal bus, accessible by core and non-core bus masters (e.g., DMA, FEC) Fast Ethern.