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SiHF740AS Dataheets PDF



Part Number SiHF740AS
Manufacturers Vishay Siliconix
Logo Vishay Siliconix
Description Power MOSFET
Datasheet SiHF740AS DatasheetSiHF740AS Datasheet (PDF)

IRF740AS, SiHF740AS, IRF740AL, SiHF740AL Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration 400 VGS = 10 V 36 9.9 16 Single I2PAK (TO-262) D2PAK (TO-263) 0.55 D G DS G D S G S N-Channel MOSFET FEATURES • Halogen-free According to IEC 61249-2-21 Definition • Low Gate Charge Qg Results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness • Fully Characterized Capacitance and Avalanche Voltage an.

  SiHF740AS   SiHF740AS


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IRF740AS, SiHF740AS, IRF740AL, SiHF740AL Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) () Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration 400 VGS = 10 V 36 9.9 16 Single I2PAK (TO-262) D2PAK (TO-263) 0.55 D G DS G D S G S N-Channel MOSFET FEATURES • Halogen-free According to IEC 61249-2-21 Definition • Low Gate Charge Qg Results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness • Fully Characterized Capacitance and Avalanche Voltage and Current • Effective Coss specified • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • Switch Mode Power Supply (SMPS) • Uninterruptible Power Supply • High speed Power Switching TYPICAL SMPS TOPOLOGIES • Single Transistor Flyback Xfmr. Reset • Single Transistor Forward Xfmr. Reset (Both for US Line Input Only) ORDERING INFORMATION Package D2PAK (TO-263) Lead (Pb)-free and Halogen-free SiHF740AS-GE3 Lead (Pb)-free IRF740ASPbF SiHF740AS-E3 Note a. See device orientation. D2PAK (TO-263) SiHF740ASTRL-GE3a IRF740ASTRLPbFa SiHF740ASTL-E3a D2PAK (TO-263) SiHF740ASTRR-GE3a IRF740ASTRRPbFa SiHF740ASTR-E3a I2PAK (TO-262) SiHF740AL-GE3 IRF740ALPbF SiHF740AL-E3 ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL Drain-Source Voltage Gate-Source Voltage Continuous Drain Currente Pulsed Drain Currenta, e VGS at 10 V TC = 25 °C TC = 100 °C Linear Derating Factor Single Pulse Avalanche Energyb, e Avalanche Currenta Repetiitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc, e TA = 25 °C TC = 25 °C Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) for 10 s VDS VGS ID IDM EAS IAR EAR PD dV/dt TJ, Tstg Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 12.6 mH, Rg = 25 , IAS = 10 A (see fig. 12). c. ISD  10 A, dI/dt  330 A/μs, VDD  VDS, TJ  150 °C. d. 1.6 mm from case. e. Uses IRF740A, SiHF740A data and test conditions. LIMIT 400 ± 30 10 6.3 40 1.0 630 10 12.5 3.1 125 5.9 - 55 to + 150 300d UNIT V A W/°C mJ A mJ W V/ns °C * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91052 S11-1048-Rev. C, 30-May-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF740AS, SiHF740AS, IRF740AL, SiHF740AL Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL Maximum Junction-to-Ambient (PCB Mounted, Steady-State)a RthJA Maximum Junction-to-Case (Drain) RthJC Note a. When mounted on 1" square PCB (FR-4 or G-10 material). TYP. - MAX. 40 1.0 UNIT °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic VDS VDS/TJ VGS(th) IGSS IDSS RDS(on) gfs VGS = 0, ID = 250 μA Reference to 25 °C, ID = 1 mAd VDS = VGS, ID = 250 μA VGS = ± 30 V VDS = 400 V, VGS = 0 V VDS = 320 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 6.0 Ab VDS = 50 V, ID = 6.0 Ad 400 - -V - 0.48 - V/°C 2.0 - 4.0 V - - ± 100 nA - - 25 μA - - 250 - - 0.55  4.9 - -S Input Capacitance Output Capacitance Reverse Transfer Capacitance Ciss Coss Crss Output Capacitance Coss Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Coss eff. Qg Qgs Qgd td(on) tr td(off) tf VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5d VGS = 0 V VDS = 1.0 V, f = 1.0 MHz VDS = 320 V, f = 1.0 MHz VDS = 0 V to 320 Vc, d VGS = 10 V ID = 10 A, VDS = 320 V, see fig. 6 and 13b, d VDD = 200 V, ID = 10 A, Rg = 10 , RD = 19.5 , see fig. 10b, d - 1030 170 7.7 1490 52 61 10 35 24 22 36 9.9 16 - pF nC ns Continuous Source-Drain Diode Current IS MOSFET symbol showing the Pulsed Diode Forward Currenta integral reverse ISM p - n junction diode D G S - - 10 A - - 40 Body Diode Voltage VSD TJ = 25 °C, IS = 10 A, VGS = 0 Vb - - 2.0 V Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge trr TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μsb, d - 240 360 ns Qrr - 1.9 2.9 μC Forward Turn-On Time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width  300 μs; duty cycle  2 %. c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS. d. Uses IRF740A, SiHF740A data and test conditions. www.vishay.com 2 Document Number: 91052 S11-1048-Rev. C, 30-May-11 This document is subject to change without.


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